Toshiya Asai

Vulnerability Evaluation Method Considering Power Supply Environment for Power Analysis Attacks

At present, encryption hardware handling confidential information of integrated circuit (IC) cards or the similar are widely available. Confidential information is protected by encryption algorithms, and its safety is computationally secured. However, the problem of power analysis attacks has been actualized. Power analysis attacks acquire confidential information based on information of power consumption leaked from cryptographic circuits that are embedded in hardware. Therefore, when designing cryptographic circuits, resistance against side-channel attacks must be evaluated. The present study proposes a method to verify the resistance including power supply environment. The present study also verifies the validity of the proposed method through several evaluation experiments.

Tamper Resistance Verification Method for Consumer Security Products

Consumer security products handling confidential information are secured by encrypting data. The encryption standard, which has been widely diffused in recent years, is certified that its decryption is computationally impossible. However, it was recently reported that even if an encryption algorithm is theoretically secured, when the algorithm is incorporated into hardware, confidential information about the algorithm could be improperly revealed using power consumption data when the hardware is operated. Such improper specifications are generally called side-channel attacks. Therefore, when an encryption algorithm is incorporated into hardware, evaluation of the resistance against power analysis attacks (tamper resistance) becomes important in the design stage of the circuit. The present study proposes a new method for efficient verification of tamper resistance against power analysis attacks when designing a cryptography circuit. The validity of the proposed method is confirmed using design data of an experimentally produced chip of the advanced encryption standard (AES).

Platform for Verification of Electromagnetic Analysis Attacks against Cryptographic Circuits

The threat of electromagnetic analysis attacks against cryptographic circuits is now becoming more evident. Therefore, it is important to evaluate the resistance of cryptographic circuits to electromagnetic analysis attacks at the design stage. In order to analyze electromagnetic waves at the design stage, an electromagnetic field simulator must be used. However, since electromagnetic analysis attacks use many waveforms, the use of an electromagnetic field simulator is not realistic from the standpoint of the processing time. The present study develops a verification platform to evaluate the vulnerability of cryptographic circuits to electromagnetic analysis attacks at the design stage. In the present study, a macro model for each element to be attacked is prepared. Using the results obtained by simulating each macro model and current, high-speed electromagnetic wave analysis is realized. The validity of the proposed method is verified by performing evaluation experiments.

Malicious Attacks on Electronic Systems and VLSIs for Security

In this chapter, we briefly review malicious attacks that have been attempted on security-critical systems employing a variety of methods, and discuss cryptographic functions embedded in VLSIs to be used in systems which require dependability in terms of protection against attackers. Recent cryptographic algorithms such as AES or RSA are computationally safe in the sense that it is practically impossible to reveal the key information from a pair of plain and cipher texts if a key with a sufficient length is used. An attacker would therefore try to reveal the cryptographic keys by exploiting possible implementation flaws in the security LSIs. For example, attempts have been made to modify the control flow of a program and read out the key data. Other types of attacks have used side-channel information such as power traces or electromagnetic emission from the LSIs. Therefore, of the utmost importance in security LSIs is “tamper resistance” or robust key-protection mechanisms. In Sect. 10.1, the role of LSIs in the integrity of security-critical systems is presented and a review is given over reported incidents of malicious attacks. Section 10.2 discusses typical tampering methods against cryptographic circuits in more detail. Tamper-resistant security hardware design and verification methods are introduced in Sects. 10.3 and 10.4. The vulnerability of scan-based test scheme is discussed in Sect. 10.5. A testing environment called SASEBO (http://www.toptdc.com/product/sasebo/) for evaluation of security LSIs is introduced in Sect. 10.6.

Frequency Domain Aware Power Analysis Attack against Random Clock LSI for Secure Automotive Embedded Systems

For road-to-vehicle and inter-vehicle communications systems, it is important to develop technologies, such as a communication channel; it is also important to develop technologies that will ensure the security of those communications. As a type of technology to satisfy the requirement, the random clock LSI, which is one of the most popular tamper resistance LSIs, has been reported. To evaluate the tamper resistance for the automotive embedded system using the random clock LSI, this study proposes an alignment method. Experiments using an actual device verify the validity of the proposed method.

Power analysis for clock fluctuation LSI

Several measures against power analysis attacks have been proposed. A clock fluctuation LSI, which achieves tamper resistance against electromagnetic analysis attacks, is one of popular measures. The present study proposes an alignment method which can analyze the clock fluctuation LSI. The proposed method corrects a shift of power consumption waveforms in the time axis direction caused by periodic fluctuation of clocks. Evaluation experiments using an actual device prove the validity of the proposed method.