Masayoshi Yoshimura

A test point insertion method to reduce the number of test patterns

The recent advances in semiconductor integration technology have resulted in an increasing number of the test lengths of full scan designed LSI. This paper presents a test point insertion method for reducing test patterns of full scan designed LSI. In our method, test points are inserted based on improved fault detection probability and value assignment probability such that test patterns are efficiently compacted. Experimental results for some practical designs show that the rate of test pattern compaction ranges from 31% to 65%. Those results also prove that our method is very effective for reducing the number of test patterns.

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times

As an LSI is on the two-dimensional plane, the number of external pins of an LSI does not equally increase to the number of gates. Therefore, the number of flip-flops on a scan path is relatively increasing. As the results, the test application time becomes longer. In this paper, three new DFT strategies are proposed to reduce the test application time. Experimental results showed the DFT strategies reduced the test application times by 46 to 82% compared with a conventional full scan design method.

Neutron-induced soft error rate estimation for SRAM using PHITS

This paper presents a novel neutron-induced soft-error-rate (SER) estimation tool with a particle transport code: PHITS. The proposed tool can calculate the SER according to various data patterns and the layout of the memory cells in an SRAM. As layouts, two kinds of an NMOS-PMOS-NMOS 6T and an inside-out PMOS-NMOS-PMOS versions are considered. The proposed tool distinguishes a single-event-upset (SEU) SER, a horizontal multiple-cell-upset (MCU) SER, and a vertical MCU SER using an extracting function. The horizontal MCU SER in the inside-out version of the PMOS-NMOS-PMOS 6T SRAM cell layout was expected to be 26-41% less than that of the general NMOS-PMOS-NMOS 6T cell layout.

Efficient Fault Simulation Algorithms for Analyzing Soft Error Propagation in Sequential Circuits

This paper presents two acceleration techniques of fault simulation for analyzing soft error propagation in sequential circuits. One is an exact technique and the other is a heuristic technique. Since these techniques are independent on how the logic functions of circuits are evaluated, they can be combined with other techniques which accelerate evaluations of the logic functions of circuits, such as event-driven simulation, single pattern parallel fault propagation (SPPFP). Experimental results show that applying the exact technique makes a fault simulator with event-driven simulation and SPPFP 30–143 times faster. A fault simulator with the exact technique finished for several large-scale circuits in 4.6 hours or less, while a fault simulator without the exact technique could not finish for such circuits in 72 hours. Furthermore, applying the heuristic technique makes a fault simulator with the exact technique about 7–17 times faster with only 0.5–2.2% estimation error.

Methodology for early estimation of hierarchical routing resources in 3D FPGAs

Power becomes an ever-increasing concern due to the growing design complexity and the shrinking process technology. Power estimation at an early stage of electronic design automation (EDA) flow is essential in order to handle the design issues much earlier. Also power due to the routing resources is a dominant in field-programmable gate arrays (FPGAs). In this paper, we introduce a methodology for early estimation of hierarchical routing resources targeting power-aware EDA flow for three-dimensional FPGAs. We analyze the behavior of wire segments on a two-dimensional plane to derive a model for estimating the required number of routing segments in a 3D FPGA for a given circuit. For a number of MCNC benchmark circuits, the proposed methodology is validated against the output of TPR, an academic 3D place and route tool for FPGAs. We achieved a mean error of 29.04% for segmented wires; single-length, double-length and hex-length segments among all 14 selected benchmark circuits.

An estimation of encryption LSI testability against scan-based attack

Recently, encryption LSIs are embedded in a variety of digital products for security and copyright protection. Most LSIs including encryption LSIs have scan paths for manufacturing tests. However, there is a risk that the secret information is leaked through scan paths. It is necessary to prevent side channel attacks to encryption LSIs. In this paper, we show all the factors for scan-based attacks to encryption LSIs. We propose a countermeasure that encryption LSIs are added to controllability and observability as possible under the condition that encryption LSI does not have all the factors which are necessary for scan-based attacks. We insert various structures of scan paths in DES chips and estimate testability and security of DES chips In addition, we propose the countermeasure against the scan-based attacks, and estimate the countermeasure from the viewpoints of testability and security. We show the trade-off between testability and security for various structures of scan path. The proposed countermeasure can achieve about 98% of high fault efficiency with preventing scan-based attack.

Malicious Attacks on Electronic Systems and VLSIs for Security

In this chapter, we briefly review malicious attacks that have been attempted on security-critical systems employing a variety of methods, and discuss cryptographic functions embedded in VLSIs to be used in systems which require dependability in terms of protection against attackers. Recent cryptographic algorithms such as AES or RSA are computationally safe in the sense that it is practically impossible to reveal the key information from a pair of plain and cipher texts if a key with a sufficient length is used. An attacker would therefore try to reveal the cryptographic keys by exploiting possible implementation flaws in the security LSIs. For example, attempts have been made to modify the control flow of a program and read out the key data. Other types of attacks have used side-channel information such as power traces or electromagnetic emission from the LSIs. Therefore, of the utmost importance in security LSIs is “tamper resistance” or robust key-protection mechanisms. In Sect. 10.1, the role of LSIs in the integrity of security-critical systems is presented and a review is given over reported incidents of malicious attacks. Section 10.2 discusses typical tampering methods against cryptographic circuits in more detail. Tamper-resistant security hardware design and verification methods are introduced in Sects. 10.3 and 10.4. The vulnerability of scan-based test scheme is discussed in Sect. 10.5. A testing environment called SASEBO (http://www.toptdc.com/product/sasebo/) for evaluation of security LSIs is introduced in Sect. 10.6.

A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations

Recently, the increased utilization of outsourcing services for a part of designing VLSIs might reduce the reliability of VLSIs. There is a risk that hardware Trojan circuits are inserted into VLSIs by attackers at design phases. It is difficult to detect Trojan circuits by functional verification and testing. In this paper, we propose a hardware Trojan circuit detection method based on a pair of non-transition lines and unset values generated as the results of acceptance verification.

Controller augmentation and test point insertion at RTL for concurrent operational unit testing

Test point insertion methods to reduce the number of test patterns at register transfer level are required for the adaptability of traditional VLSI design flows and the reduction of time to search test point locations. In this paper, we propose a design-for-testability method at register transfer level to enable operational units as many as possible to be concurrently tested in scan testing. Using test point insertion and controller augmentation, the proposed design-for-testability method allocates input test registers and an output test register to inputs and an output of each operational unit in a data-path, respectively. Test compaction efficiency becomes high by enabling effective concurrent testing for operational units. Experimental results on high-level benchmark circuits show that our proposed method reduced the number of test patterns by 20% with 6.5 % area overhead on average.