Toshiyuki Mine

A poly-silicon TFT with a sub-5-nm thick channel for low-power gain cell memory in mobile applications

This work presents a gain-cell solution in which a novel ultrathin polysilicon film transistor provides the basis for dense and low-power embedded random-access memory (RAM). This is made possible by the new transistors 2-nm-thick channel, which realizes a quantum-confinement effect that produces a low leakage current value of only 10/sup -19/ A at room temperature. The memory has the potential to solve the power and stability problems that static RAM (SRAM) is going to face in the very near future.

Advanced TFT SRAM cell technology using a phase-shift lithography

An advanced TFT memory cell technology has been developed for making high-density and high-speed SRAM cells. The cell is fabricated using a phase-shift lithography that enables patterns with spaces of less than 0.25 /spl mu/m to be made using the conventional stepper. Cell area is also reduced by using a small cell-ratio and a parallel layout for the transistor. Despite the small cell-ratio, stable operation is assured by using advanced polysilicon PMOS TFTs for load devices. The effect of the Si/sub 3/N/sub 4/ multilayer gate insulator on the on-current and the influence of the channel implantation are also investigated. To obtain stable operation and extremely low stand-by power dissipation, a self-aligned offset structure for the polysilicon PMOS TFT is proposed and demonstrated. A leakage current of only 2 fA/cell and an on-/off-current ratio of 4.6/spl times/10/sup 6/ are achieved with this polysilicon PMOS TFT in a memory cell, which is demonstrated in a experimental 1-Mbit CMOS SRAM chip that has an access time of only 7 ns. >

Negative bias temperature instability of pMOSFETs with ultra-thin SiON gate dielectrics

The negative bias temperature instability (NBTI) of pMOSFETs with ultra-thin gate dielectrics was investigated from four points of view: basic mechanism of NBTI, dependence of NBTI on gate dielectric thickness, mechanism of NBTI enhancement caused by addition of nitrogen to the gate dielectrics, and possibility of applying SiON gate dielectrics with a high concentration of nitrogen. By investigating the behavior of FET characteristics after NBT stresses were stopped, it was clarified that a portion (60%, in our case) of hydrogen atoms released by the NBT stress remains in the gate dielectric in the case of a 1.85-nm-thick NO-oxynitride gate dielectric. The existence of the hydrogen was shown to lead to the generation of positive fixed charges in the gate dielectric. It was also found that NBTI depends little on gate dielectric thickness. Moreover, we revealed that the origin of NBTI enhancement by incorporating nitrogen into gate dielectrics is the property of attracting H/sub 2/O or OH. We speculate that this property is due to the existence of positive fixed charges induced by undesirable nitrogen. We evaluated NBTI immunity of SiN gate dielectrics with an oxygen-enriched interface (OI-SiN) in which high carrier mobility was obtained by reducing positive fixed charges. OI-SiN gate dielectrics with EOTs of 1.4 and 1.6 nm were found to have sufficient lifetime for practical use under 1 V operation.

Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM

The impact of a random telegraph noise (RTN) on a scaled-down SRAM is shown for the first time. To estimate the impact on SRAM, we statistically analyzed a threshold voltage fluctuation (DeltaVth) of n-and p-MOSFETs. It is revealed that DeltaVth of the p-MOSFET is larger than that of the n-MOSFET. This difference can be explained by considering the followings: (i) number- and mobility-fluctuation models of RTN (ii) the difference in the capture cross section between electron and hole. In addition, based on these results, SRAM margin enclosed by read / write Vth curves with or without RTN was simulated. We consequently found that Vth margin comes close to Vth window of the SRAM by considering the effect of RTN on DeltaVth, even at hp 65. Moreover, DeltaVth due to RTN of the p-MOSFET is comparable with DeltaVth due to the random dopant fluctuation (RDF) at hp 45 because DeltaVth due to the RDF is inversely proportional to square root of the gate area (S), while DeltaVth due to RTN is inversely proportional to S.

A novel MNOS technology using gate hole injection in erase operation for embedded nonvolatile memory applications

A novel MNOS memory with gate hole injection in erase operation has been demonstrated for embedded nonvolatile memory applications. Superior characteristics with 10/spl mu/sec programming and 10msec erasing speed were obtained as compared with conventional MONOS structures. In addition, we found that the localized interface trap at source side region was generated by excess holes during erasing cycle and could be suppressed by Lg scaling. This result shows the good scalability of this technology.

Electro-luminescence from ultra-thin silicon

Ultra-thin single crystal silicon with the (100) surface formed by the local-oxidation-of-silicon (LOCOS) on a silicon-on-insulator (SOI) substrate becomes a quasi-direct band-gap semiconductor due to the quantum mechanical confinement effect. The device is a simple pn diode in a planar structure. Electro-luminescence (EL) has been observed by the lateral carrier injections into the two-dimensional quantum well.

Silicon light-emitting transistor for on-chip optical interconnection

The authors propose a light-emitting field-effect transistor with the active layer made of the ultrathin single crystal silicon with the (100) surface orientation. The ambipolar carrier injections from the highly impurity doped regions to the ultrathin silicon are achieved in complementary-metal-oxide-semiconductor compatible planar structures and the optical intensities are controlled by the gate voltage. By using the device, they have demonstrated that a simple electrical signal can be transferred by light and detected on the same silicon chip as photocurrents controlled by the gate bias.

Effects of remote-surface-roughness scattering on carrier mobility in field-effect-transistors with ultrathin gate dielectrics

We examined effects of the remote surface roughness, which is the roughness between the polycrystalline silicon gate and gate dielectric, on the inversion carrier mobility of metal-insulator-semiconductor field-effect-transistors with ultrathin gate dielectrics. We calculated the effective mobility by the linear response theory and found that the scattering from the remote surface roughness reduces the effective mobility especially at high vertical fields. The effective mobility is severely reduced, if the correlation length of the remote surface roughness is comparable to the inverse of thermal de Broglie wave number. We show that the hole mobility reduction experimentally found for the transistor with the Al2O3 gate dielectric can be explained by this scattering.

Single-electron-memory integrated circuit for giga-to-tera bit storage

A single-electron-based integrated circuit is presented. An 8/spl times/8 b memory-cell array demonstrates read/write, ushering in a new phase of research on single-electron devices.

Stimulated emission of near-infrared radiation by current injection into silicon (100) quantum well

We describe the observation of stimulated emissions by current injections into a silicon quantum well. The device consists of a free standing membrane with a distributed feedback resonant cavity fabricated by state-of-the-art silicon processes. The emission spectra have multimode structures peaked in the near-infrared region above the submilliampere threshold currents at room temperatures. Consequently, electronics and photonics should be able to be converged on chips by using silicon quantum well laser diodes.