Toshiyuki Tabata

Ge/GeO2 Interface Control with High-Pressure Oxidation for Improving Electrical Characteristics

High-pressure oxidation (HPO) of germanium (Ge) for improving electrical properties of Ge/GeO2 stacks was investigated. The capacitance–voltage (C–V) characteristics of metal/GeO2/Ge capacitors fabricated with HPO revealed improved electrical properties without any post-deposition annealing, and the interface states density (Dit) was reduced to 2×1011 eV-1 cm-2 near the midgap. Moreover, the refractive index of thermally oxidized GeO2 was increased by HPO. It is also discussed from a thermodynamic viewpoint of the Ge/GeO2 system that the GeO desorption from Ge/GeO2 stacks could be efficiently suppressed by HPO.

Desorption kinetics of GeO from GeO2/Ge structure

High-κ dielectrics on Ge have recently attracted much attention as a potential candidate to replace planar silicon transistors for sub-32-nm generations. However, the instability of the high-κ/Ge interface, especially the desorption of germanium monoxide (GeO), hampers the development of Ge-based devices. Therefore, the typical GeO2/Ge structure was chosen to investigate GeO desorption. In this contribution, we describe the desorption kinetics of GeO, including Ge/GeO2 interface reaction, the diffusion process during GeO desorption, the desorption activation energy of GeO, the different mechanisms of GeO desorption, and the active oxidation of Ge. Through annealing GeO2/Ge in an ultrahigh vacuum (UHV), direct evidence for the consumption of Ge substrate has been shown by atomic force microscopy (AFM) measurements of the consumption depth. By using thermal desorption spectroscopy (TDS) measurements and studying oxygen-18 isotope tracing, we have clarified that the GeO desorption is not caused by the GeO di...

High-Electron-Mobility Ge n-Channel Metal?Oxide?Semiconductor Field-Effect Transistors with High-Pressure Oxidized Y2O3

This letter presents a significant improvement of electron mobility in a germanium (Ge) n-channel metal–oxide–semiconductor field-effect transistor with a yttrium oxide (Y2O3) gate dielectric film annealed in high-pressure O2. Interface state density in the upper half of the band gap is reduced to 1011 cm-2 eV-1 and the peak effective mobility is increased up to 1,500 cm2 V-1 s-1. This mobility enhancement is attributed to the suppression of GeO desorption or to passivation of the imperfect interface GeO2 layer by diffused Y2O3. There is no temperature dependence of the observed mobility, which suggests that intrinsic phonon scattering is still not dominant.

Material potential and scalability challenges of germanium CMOS

This paper overviews the present status of Ge MOSFET technology, particularly focusing on n-FETs in terms of materials science of GeO2/Ge gate stacks and device physics of inversion layer mobility, and then discusses future prospects and fundamental challenges for further miniaturization from the viewpoint of Ge/high-k gate stacks and ET-GeOI MOSFETs.

Characterization of electron mobility in ultrathin body germanium-on-insulator metal-insulator-semiconductor field-effect transistors

We have systematically investigated electron mobility behaviors in germanium-on-insulator (GeOI) metal-oxide-semiconductor field-effect transistors (MOSFETs) with reducing the Ge channel thickness down to 9 nm. 9 nm-thick GeOI n-MOSFETs operated with a reasonable Ion/Ioff ratio of ∼105, but it showed the electron mobility degradation compared with thick GeOI case. To investigate the physical origin of the mobility degradation in ultrathin body (UTB) GeOI n-MOSFETs, the depth profiling of GeOI crystallinity was investigated by Raman spectroscopy. A difference of Ge crystallinity in the front channel from that in back one was discussed to explain the mobility degradation in UTB region.

Impact of High Pressure O2 Annealing on Amorphous LaLuO3/Ge MIS Capacitors

Amorphous LaLuO3/Ge MIS capacitors were fabricated and dielectric properties were investigated. LaLuO3 has a high dielectric constant (k~23) and an amorphous structure after annealed at 600oC. Its energy band-gap is reasonably large (5.5~5.8 eV). The C-V characteristics annealed in a small amount of O2 ambient were quite good and showed a high saturated capacitance thanks to a negligible interface layer formation. Furthermore, it has been demonstrated that the hysteresis in C-V curves was reduced by high pressure O2 annealing. Although an optimization of the trade-off between EOT increase and hysteresis reduction will be the next challenge for LaLuO3 on Ge, the high pressure O2 annealing will make a strong combination with amorphous LaLuO3.

Oxidation Rate Reduction of Ge with O2 Pressure Increase

We report that the oxidation rate of Ge is reduced as the oxygen pressure increases below 520 °C, which is regarded as low-temperature high-pressure oxidation (LT-HPO). This result has never been observed in Si. In addition to new results, the density increase of GeO2 has been identified from the analysis of the etching rate and X-ray reflection measurements. Furthermore, the equivalent oxide thickness = 1.2 nm of GeO2/Ge stack with excellent gate leakage current properties has been achieved by this method. To explain this phenomenon, a simple kinetic model of Ge oxidation is also discussed.

Experimental study of carrier transport in ultra-thin body GeOI MOSFETs

We have investigated carrier transport properties in ultra-thin body (UTB) Ge-on-Insulator (GeOI) MOSFETs for the first time. Both n- and p-channel MOSFET operation fabricated on 9 nm GeOI has been demonstrated. In addition, a significant difference of Ge crystallinity in the front-channel from that in back-one is reported to explain the mobility degradation in UTB region.

Effect of High-Pressure Inert Gas Annealing on AlON/Ge Gate Stacks

We investigated germanium (Ge) metal–insulator–semiconductor (MIS) gate stacks with aluminum oxynitride (AlON) thin dielectric film. We found that high-pressure inert gas post deposition annealing (PDA) using N2 or Ar gas dramatically improved the electrical properties of AlON/Ge MIS gate stacks. The advantage of this process over high-pressure O2 oxidation or annealing, which produce excellent Ge gate stacks, is that no further interface layer growth in the N2 or Ar PDA is expected. We expect that thin AlON films combined with high-pressure inert gas PDA will provide a new way to achieve excellent Ge-MIS gate stacks with scalable equivalent oxide thickness.

Variation of Surface Roughness on Ge Substrate by Cleaning in Deionized Water and its Influence on Electrical Properties in Ge Metal–Oxide–Semiconductor Field-Effect Transistors

The control of Ge surface roughness using deionized water (DIW) was systematically investigated. It was found that a very flat surface was obtained by pure-DIW dipping at room temperature, while quite a rough surface was observed at high temperature. The surface reaction model of Ge with H2O is proposed to explain the correlation of surface roughness (SR) formation with the etching process of Ge in DIW. In addition, the effects of SR on electrical properties in Ge/GeO2 stack such as capacitance–voltage (C–V) curves, interface state density, and electron mobility are presented.