Toshiyuki Uchino

Process integration of single-wafer technology in a 300-mm fab, realizing drastic cycle time reduction with high yield and excellent reliability

In this paper, we discuss a new technology implemented with single-wafer processing for a 300-mm fab. Newly developed equipment and chemicals reduce the process time and provide cost savings. The combination of fully automated systems and single-wafer processing significantly reduces queuing time. The process has been re-integrated to eliminate long time processes and make it suitable for single-wafer technologies. As a result, a very aggressive cycle time (0.25 days/layer) with high yield, in double-polysilicon, sextuple-metal, 0.18-/spl mu/m logic process has been demonstrated. High-performance devices with excellent reliability are also obtained. A new methodology for detecting parametric errors effectively in the early stages of production is implemented for quick yield ramp up.

Temperature distribution in semiconductor wafers heated in a vertical diffusion furnace

The transient temperature distribution in a row of wafers heating in a vertical diffusion furnace was calculated as the heating power of the furnace was PID (proportional plus integral plus derivative) controlled. Radiative heat transfer was combined with axisymmetric unsteady conduction in wafers and the furnace. With feedforward control of the heating power (which means that when wafers are inserted into the furnace, the heater temperature is set higher than the desired heating temperature), the temperature of the wafers reached the heating temperature rapidly. The radiative properties of silicon wafers changed from semitransparent to opaque at 500 degrees C, and the effect of this change on the temperature distribution in the wafers was calculated. Thermoplastic deformation of the wafers is more likely to occur during withdrawal than during insertion.<<ETX>>

Temperature distribution in semiconductor wafers heated in a hot-wall-type rapid diffusion furnace

Transient temperature distribution was calculated for wafers heated in a new hot-wall-type rapid diffusion furnace. Two-dimensional radiative heat transfer was combined with unsteady conduction in wafers and the furnace. The furnace is composed of parallel plate heaters, and heats wafers to a temperature of about 1000/spl deg/C. The heaters are divided into four zones and their heating powers are PID-controlled. Two wafers on a holder are inserted vertically from the bottom of the furnace, and heated for three minutes. The calculated results show the wafer temperature approached the desired heating temperature about one minute after insertion, agreeing with experimental results. The average temperature distribution in the wafers during heating is found to be within /spl plusmn/1/spl deg/C at 1000/spl deg/C, when the heating power (temperature) of the four zones is properly controlled. The effects of heater temperature, insertion speed, and holder thickness on the temperature distribution in wafers were calculated. The new hot-wall-type rapid diffusion furnace can be used to manufacture future VLSI.<<ETX>>