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Featured researches published by Atsuyoshi Koike.


international symposium on semiconductor manufacturing | 2004

High-speed AMHS and its operation method for 300-mm QTAT fab

Takayuki Wakabayashi; Shinichi Watanabe; Yoshiaki Kobayashi; Tsutomu Okabe; Atsuyoshi Koike

By using all-single-wafer processing in the 300-mm quick turn-around time production system, we have shortened cycle time to one-half or less than that of mixed-batch processing. We have also developed a high-speed automated material handling systems (AMHS) for achieving short cycle time. An intrabay rail-guided vehicle developed for the 300-mm fab is a component of this system. This paper describes the new system concepts, including AMHS hardware improvement, operation methods, and technician skill enhancement. We achieved a transfer time of one third or less that of previous fabs.


IEEE Journal of Solid-state Circuits | 1994

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

Koichiro Ishibashi; Kunihiro Komiyaji; S. Morita; T. Aoto; Shuji Ikeda; K. Asayama; Atsuyoshi Koike; Toshiaki Yamanaka; Norikazu Hashimoto; H. Iida; F. Kojima; K. Motohashi; Katsuro Sasaki

A 16-Mb CMOS SRAM using 0.4-/spl mu/m CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm/sup 2/ is fabricated and an address access time of 12.5 ns has been achieved. >


IEEE Transactions on Semiconductor Manufacturing | 2003

Process integration of single-wafer technology in a 300-mm fab, realizing drastic cycle time reduction with high yield and excellent reliability

Shuji Ikeda; Kazunori Nemoto; Michimasa Funabashi; Toshiyuki Uchino; Hirohiko Yamamoto; Noriyuki Yabuoshi; Yasushi Sasaki; Kazuhiro Komori; Norio Suzuki; Shinji Nishihara; Shunji Sasabe; Atsuyoshi Koike

In this paper, we discuss a new technology implemented with single-wafer processing for a 300-mm fab. Newly developed equipment and chemicals reduce the process time and provide cost savings. The combination of fully automated systems and single-wafer processing significantly reduces queuing time. The process has been re-integrated to eliminate long time processes and make it suitable for single-wafer technologies. As a result, a very aggressive cycle time (0.25 days/layer) with high yield, in double-polysilicon, sextuple-metal, 0.18-/spl mu/m logic process has been demonstrated. High-performance devices with excellent reliability are also obtained. A new methodology for detecting parametric errors effectively in the early stages of production is implemented for quick yield ramp up.


international solid-state circuits conference | 1990

A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current

Katsuro Sasaki; Koichiro Ishibashi; Katsuhiro Shimohigashi; Toshiaki Yamanaka; N. Moriwake; Shigeru Honjo; Shuji Ikeda; Atsuyoshi Koike; Satoshi Meguro; Osamu Minato

A 4-Mb (512 K*8) CMOS SRAM that uses a 0.5- mu m quadruple-poly double-metal CMOS technology to attain 23-ns address access time with a single 5-V external supply voltage and a load capacitance of 30 pF is described. Current-mirror/PMOS cross-coupled cascade sense amplifier circuits with a noise-immune data-latch circuit are used. A polysilicon PMOS load memory cell enables a 0.5- mu A standby current (V/sub cc/=3 V) with a 17- mu m/sup 2/ memory cell area. A 122-mm/sup 2/ (7.2*16.9-mm) chip is achieved by the double-array word-decoder architecture.<<ETX>>


international symposium on semiconductor manufacturing | 1995

A new LSI manufacturing scheme in the large-diameter wafer era for super-quick TAT development and volume production

Atsuyoshi Koike; S. Shimoyashiro; K. Kubota; N. Suzuki; Y. Kiguchi; A. Fujisawa; A. Takamatsu; T. Okabe

We describe a new LSI manufacturing scheme which features the compatibility of quick TAT development and volume production. It is composed of a main production line and extra paths of single-wafer processing. In the super-quick TAT runs, all of the batch process steps in the main line are replaced by single-wafer processing. The process compatibility enables us to smoothly transfer from development to volume production. We discuss implementation issues, and show experimental and simulation results to verify the effectiveness of this concept in the development of logic and memory products. This approach will reduce the cost for process development, and enhance the evolution of single-wafer processing equipment towards the large-diameter wafer era.


Characterization and Metrology for ULSI Technology | 1998

Metrology issues for processing of 300 mm wafers

Kenji Watanabe; Atsuyoshi Koike

Construction of IC lines using 300 mm wafers will begin in 1998–99 for pilot lines, with construction of mass production lines in 2000 or later. These lines will most likely be introduced with design rules in the range from 250 to 180 nm. Difficult challenges for these feature sizes include critical dimensions, registration, thin film measurement, and defect inspection. At the same time, metrology is expected to play a major role in controlling costs, increasing manufacturing flexibility, and decreasing cycle time in addition to assisting in the reduced emission of global warming gases.


Archive | 1995

SRAM having load transistor formed above driver transistor

Shuji Ikeda; Satoshi Meguro; Soichiro Hashiba; Isamu Kuramoto; Atsuyoshi Koike; Katsuro Sasaki; Koichiro Ishibashi; Toshiaki Yamanaka; Naotaka Hashimoto; Nobuyuki Moriwaki; Shigeru Takahashi; Atsushi Hiraishi; Yutaka Kobayashi; Seigou Yukutake


Archive | 1996

Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same

Jun Murata; Yoshitaka Tadaki; Hiroko Kaneko; Toshihiro Sekiguchi; Hiroyuki Uchiyama; Hisashi Nakamura; Toshio Maeda; Osamu Kasahara; Hiromichi Enami; Atsushi Ogishima; Masaki Nagao; Michimasa Funabashi; Yasuo Kiguchi; Masayuki Kojima; Atsuyoshi Koike; Hiroyuki Miyazawa; Masato Sadaoka; Kazuya Kadota; Tadashi Chikahara; Kazuo Nojiri; Yutaka Kobayashi


Archive | 1991

SRAM with dual word lines overlapping drive transistor gates

Shuji Ikeda; Satoshi Meguro; Soichiro Hashiba; Isamu Kuramoto; Atsuyoshi Koike; Katsuro Sasaki; Koichiro Ishibashi; Toshiaki Yamanaka; Naotaka Hashimoto; Nobuyuki Moriwaki


Archive | 1995

Semiconductor integrated circuit device and process for fabricating the same

Shuji Ikeda; Satoshi Meguro; Soichiro Hashiba; Isamu Kuramoto; Atsuyoshi Koike; Katsuro Sasaki; Koichiro Ishibashi; Toshiaki Yamanaka; Naotaka Hashimoto; Nobuyuki Moriwaki; Shigeru Takahashi; Atsushi Hiraishi; Yutaka Kobayashi; Seigou Yukutake

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