Trevor C. Caldwell

A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20-MHz signal bandwidth

This paper presents the first implementation results for a time-interleaved continuous-time DeltaSigma modulator. The derivation of the time-interleaved continuous-time DeltaSigma modulator from a discrete-time DeltaSigma modulator is presented. With various simplifications, the resulting modulator has only a single path of integrators, making it robust to DC offsets. A time-interleaved by 2 continuous-time third-order low-pass DeltaSigma modulator is designed in a 0.18-mum CMOS technology with an oversampling ratio of 5 at sampling frequencies of 100 and 200 MHz. Experimental results show that a signal-to-noise-plus-distortion ratio (SNDR) of 57 dB and a dynamic range of 60 dB are obtained with an input bandwidth of 10 MHz, and an SNDR of 49 dB with a dynamic range of 55 dB is attained with an input bandwidth of 20 MHz. The power consumption is 101 and 103 mW, respectively

Incremental Data Converters at Low Oversampling Ratios

In this paper the use of incremental A/D converters with low oversampling ratios is investigated. Incremental A/D converters are able to achieve a higher SQNR than delta-sigma modulators at oversampling ratios below 4, allowing them to operate as higher bandwidth converters with medium resolution. The impact of removing the input S/H, as well as analyzing their behaviour at an OSR as low as 1 is explored. An eighth-order cascaded incremental A/D converter is analyzed and shown as an example.

A time-interleaved continuous-time /spl Delta//spl Sigma/ modulator with 20MHz signal bandwidth

This paper presents the first implementation results for a time-interleaved continuous-time /spl Delta//spl Sigma/ modulator. The 3rd-order low-pass modulator operates at an oversampling ratio of 5 with a time-interleaving factor of 2 at sampling frequencies of 100MHz and 200MHz. It achieves an SNDR of 57dB and 49dB in signal bandwidths of 10MHz and 20MHz, respectively.

HIGH-SPEED OVERSAMPLING ANALOG-TO-DIGITAL CONVERTERS

This paper is mainly tutorial in nature and discusses architectures for oversampling converters with a particular emphasis on those which are well suited for high frequency input signal bandwidths. The first part of the paper looks at various architectures for discrete-time modulators and looks at their performance when attempting high speed operation. The second part of this paper presents some recent advancements in time-interleaved oversampling converters. The next section describes the design and challenges in continuous-time modulators. Finally, conclusions are made and a brief summary of the recent state of the art of high-speed converters is presented.

An Incremental Data Converter with an Oversampling Ratio of 3

At low oversampling ratios, incremental ADCs are able to achieve a higher SNR than SigmaDelta modulators, allowing them to operate at oversampling ratios as low as 2-4 with high resolution. Furthermore, the removal of the input sample-and-hold significantly reduces the power consumption of incremental ADCs while slightly altering their signal transfer function. In this paper, the new application of incremental ADCs as high-speed data converters is demonstrated. A proposed 7th-order cascaded incremental ADC is analyzed and compared to a pipeline ADC, and it is shown that an incremental ADC can save half the analog power due to the removal of the input sample-and-hold and the reduced number of stages required for 12-bit operation

An 8 th -order MASH delta-sigma with an OSR of 3

This paper demonstrates that a high-order MASH delta-sigma modulator with a very low oversampling ratio can attain performance similar to a pipelined converter. The delta-sigma architecture fabricated is an 8-stage cascade of 1st-order stages with an oversampling ratio of 3 and realized in a 0.18µm CMOS process. The modulator attains an SNDR of 60 dB at a 50MHz sampling frequency and an 8.33MHz input bandwidth.

A high-speed technique for time-interleaving continuous-time delta-sigma modulators

A technique for increasing the speed of time-interleaved continuous-time /spl Delta//spl Sigma/ modulators is presented. Extra feedback paths allow the DAC pulse to enter the adjacent clock period without deteriorating the SNR of the /spl Delta//spl Sigma/ modulator. With the added feedback paths, an extra summer needs to be added to the modulator to attain an equivalent impulse response, but the critical path of the modulator is able to operate twice as fast. Also, with the inclusion of non-idealities such as finite gain and finite bandwidth opamps and DAC clock jitter, the modulator is able to attain a higher SNR with the new technique.

Time-interleaved incremental data converters with low oversampling ratios

Incremental ADCs can operate at lower oversampling ratios than DeltaSigma modulators, resulting in higher input signal bandwidths. In this paper it is shown that time-interleaving can further increase the input signal bandwidth in incremental ADCs to the point that the oversampling ratio is equal to the time-interleaving factor, resulting in no decrease in the allowable input signal bandwidth due to oversampling. This paper investigates some of the advantages and challenges that time-interleaved incremental ADCs offer, and presents an example where a time-interleaved by 4 incremental ADC with an oversampling ratio of 4 can attain a resolution of 12 bits.

Very Low OSR Sigma-Delta Converters

This chapter investigates ΣΔ modulators and incremental A/D converters at low oversampling ratios. Both architectures have advantages at reduced OSRs; incremental A/D converters are able to achieve higher SQNR than ΣΔ modulators at oversampling ratios below 8, and ΣΔ modulators can attain better thermal noise performance than pipeline A/D converters at low OSRs. Both architectures are analyzed and a sample 8th-order cascaded architecture is demonstrated for both topologies.