Tryggve Fossum

Cache scrubbing in microprocessors: myth or necessity?

Transient faults from neutron and alpha particle strikes in large SRAM caches have become a major problem for microprocessor designers. To protect these caches, designers often use error correcting codes (ECC), which typically provide single-bit error correction and double-bit error detection (SECDED). Unfortunately, two separate strikes could still flip two different bits in the same ECC-protected word. This we call a temporal double-bit error. SECDED ECC can only detect, not correct such errors. We show how to compute the mean time to failure for temporal double-bit errors. Additionally, we show how fixed-interval scrubbing - in which error checkers periodically access cache blocks and remove single-bit errors - can mitigate such errors in processor caches. Our analysis using current soft error rates shows that only very large caches (e.g., hundreds of megabytes to gigabytes) need scrubbing to reduce the temporal double-bit error rate to a tolerable range.

On-Die Interconnect and Other Challenges for Chip-Level Multi-Processing

There is increasing interest in chip-level multi-processing, and in this talk I will discuss some the motivations, and some of the challenges in designing such chips. A key component is the on-die interconnect, and we will look at this along with some thoughts on core design, cache architecture, memory bandwidth, power management, error handling, and system scaling.

Using in-flight chains to build a scalable cache coherence protocol

As microprocessor designs integrate more cores, scalability of cache coherence protocols becomes a challenging problem. Most directory-based protocols avoid races by using blocking tag directories that can impact the performance of parallel applications. In this article, we first quantitatively demonstrate that state-of-the-art blocking protocols significantly constrain throughput at large core counts for several parallel applications. Nonblocking protocols address this throughput concern at the expense of scalability in the interconnection network or in the required resource overheads. To address this concern, we enhance nonblocking directory protocols by migrating the point of service of responses. Our approach uses in-flight chains of cores making parallel memory requests to incorporate scalability while maintaining high-throughput. The proposed cache coherence protocol called chained cache coherence, can outperform blocking protocols by up to 20% on scientific and 12% on commercial applications. It also has low resource overheads and simple address ordering requirements making it both a high-performance and scalable protocol. Furthermore, in-flight chains provide a scalable solution to building hierarchical and nonblocking tag directories as well as optimize communication latencies.

Simulating stencil-based application on future Xeon Phi processor

An important application for hydrocarbon exploration is simulated on a performance model of a novel Intel architecture. The accuracy of the simulation models is demonstrated by correlating against an existing processor first and then against high-accuracy simulation of the new architecture. The results show that key architectural features of the coming Knights Landing processor will positively impact the performance of the application.

Multi core design for chip level multiprocessing

Chip level integration continues to be a driving force in the computer industry. It lowers the cost and increases performance of computer systems, creating a remarkable rate of improvement in all processors, from handheld devices to supercomputers. Processor chips now (in 2009) contain up to two billion transistors. Gordon Moore outlined a roadmap for chip level integration in 1965, which has become known as Moores Law. It predicts that the density of transistors in a silicon chip will double every process generation. It has become the heartbeat of the semiconductor industry.