Tsan-Wen Chen

A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications

This work provides a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes include multi-tone code division multiple access (MT-CDMA) and orthogonal frequency division multiplexing (OFDM) to meet multi-user coexistence (up to 8) and high data rate purposes. Based on the analysis of the WBAN operation behavior, several methods including higher data rate, optimal storage determination, and low power implementation techniques are proposed to reduce the transmission energy. To achieve tiny area integration, an embedded phase frequency tunable clock generator and frequency error pre-calibration scheme are provided to extend the frequency mismatch tolerance to 100 ppm (2.5 x of state-of-the-art systems). This chipset is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5 V, this chipset is able to provide maximum date rate of 4.85 Mbps with modulator power consumption of 5.52 muW.

A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters

Linear amplification with nonlinear components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital signal component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06 mm2. The DCPS can generate phase-modulated signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34°). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 μW which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15° phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10° phase mismatch, the system EVM of - 29.81 dB and ACPR of - 34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM signals.

A QPSK/16-QAM OFDM-based 29.1Mbps LINC transmitter for Body Channel Communication

This paper proposed a high speed Body Channel Communication (BCC) transmitter under IF 20MHz, adopting the OFDM modulation and uneven multi-level LINC technique to reduce the power and complexity of the front-end circuit. The OFDM uses 16-QAM modulation to enhance the data rate and could select to use a convolutional code to increase the coding gain. The phase modulator in the LInear amplification with Nonlinear Component (LINC) transmitter uses not only clockgating scheme but also the glitch free protection. A detection and calibration DSP are also integrated to solve the LINC branch mismatch problem. Finally the capacitive sensing circuit provides the information of the connectivity between pastes and human. The chip is implemented by 90nm CMOS process, with die area 1.3mm2. The maximum data rate could achieve 29.1Mbps. The total power is 1.925mW, resulting in 0.07nJ/bit transmission energy and 2.92 bps/Hz spectral efficiency.

A 0.67mW 14.55Mbps OFDM-based sensor node transmitter for body channel communications

This paper presents an energy-efficient sensor node transmitter for body channel communication (BCC) system. The OFDM modulation is adopted in this work to achieve both high transmission data rate and spectrum efficiency. To reduce the power dissipation of the front-end (FE) circuits, a phase-modulated outphasing architecture is applied to avoid the power-hungry data converters and linear amplifier. Besides, the voltage scaling and balanced source gating (BSG) schemes are proposed to save the circuit active power, resulting in 81.3% reduction. The proposed sensor node transmitter chip is manufactured in 90 nm standard CMOS process with a die area 1.1016 mm2. The proposed BCC system is operated at 40 / 80 MHz with 10 MHz signal bandwidth, and the maximum data rate of 14.55 Mbps with 0.67 mW power dissipation can be achieved, leading to 0.05 nJ/b transmission energy and 1.46 bps/Hz spectral efficiency.

An OFDMA-based wireless body area network using frequency pre-calibration

A rotator and synthesizer driven (RSD) frequency pre-calibration technique is proposed in this paper for the wireless body area network applications. To overcome the large carrier frequency offset (CFO) and sampling clock offset (SCO) due to a low-cost and low-precision reference clock, the CFO and SCO are estimated from the system downlink process. These estimated CFO and SCO values are provided to a rotator and a synthesizer for signal pre-processing. This RSD concept is evaluated in the proposed WiBoC OFDMA system. The tolerated CFO and SCO ranges are extended to 2.5x of existing wireless systems. This system is designed and simulated in a 90 nm technology with 77.5 muW computation power overhead.

A low power all-digital signal component separator for uneven multi-level LINC systems

This paper presents an all-digital signal component separator (SCS) with low power overhead for uneven multilevel LINC (UMLINC) systems, including a multi-level phase calculator (MLPC) and a digitally-control phase shifter (DCPS) pair. The optimal gain level with branch mismatch consideration is proposed to achieve maximal average efficiency 44.82%. This SCS chip is manufactured in 90 nm standard CMOS process with an active area 0.5 mm2. The required phases of branch signals and PA gain controls can be calculated by the proposed MLPC. Instead of four DACs, the DCPS pair with a continuous PVT monitor is also proposed to generate the phase-modulated signals accurately at IF frequency 80 MHz with 8-bit resolution. By applying voltage scaling and source gating on DSP functions and DCPSs respectively, 81.32% power cost of SCS can be reduced, and the overall power is only 0.65 mW. With the proposed SCS, the EVM of −31.06 dB using 64-QAM OFDM signals can be achieved for high-efficiency UMLINC systems.

A sub-mW all-digital signal component separator with branch mismatch compensation for OFDM LINC transmitters

This paper presents a sub-mW all-digital signal component separator (SCS) with a novel branch mismatch compensation scheme for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. This chip is manufactured in 90nm standard CMOS process with active area 0.06mm2. The DCPS can generate phase-modulated signal at IF 100MHz with 8-bit resolution and RMS error 9.33ps (0.34°). The phase calculation can be operated with maximum 50MHz speed at 0.5V supply voltage, resulting in 73.88% power reduction, and the overall SCS power is only 949.5μW. With the aid of this SCS, the branch mismatch compensation scheme provides 0.02dB gain and 0.15° phase fine-tune resolution. The system EVM with 64-QAM OFDM signals is −29.81dB, and the spectrum can pass the mask test of IEEE 802.11a.

An energy-efficient OFDM-based baseband transceiver design for ubiquitous healthcare monitoring applications

This work proposes an orthogonal frequency division multiplexing (OFDM) based baseband transceiver design for wireless body area network (WBAN) application. Based on the analysis of the WBAN operation behavior, high transmission data rate and low power implementation techniques are proposed to reduce the transmission energy. An electrocardiography (ECG) transmission platform is also established with proposed design for system evaluation. This chip is implemented in a 90nm CMOS technology with the core size of 2.85 mm2, and this baseband transceiver dissipates 357.14 uW with supply voltage 0.5 V. The proposed chip provides maximum 9.7 Mbps data rate, resulting in active duty cycle of 0.1763% and the transmission energy of 0.37 nJ / bit.

A low-power all-digital phase modulator pair for LINC transmitters

This paper presents a low-power all-digital phase modulator (PM) pair to generate constant-envelope signals for LINC transmitters. To reduce the power overhead, an open-loop delay line based phase shifter with a continuous locking scheme is adopted for the PM design. This design is implemented by 90 nm CMOS technology with active area of 0.1892 mm2. The PM provides 8-bit resolution with RMS error 0.33° at IF frequency 80 MHz, and the power consumption is only 885 uW with 1.0 V supply voltage. Considering a 64-QAM OFDM system, the EVM of −31.87 dB can be achieved by using the proposed PM pair.

A low-power all-digital signal component separator for OFDM LINC systems

LINC can achieve linear amplification by using high-efficiency amplifiers. This work presents an all-digital LINC signal component separator (SCS) including the phase calculation digital signal processing and two digital-control phase shifters (DCPSs). With the duplicate DCPSs, a pre-calibration scheme is introduced to guarantee the codeword-to-phase linearity and accuracy under different PVT conditions. The proposed DCPS design provides 8-bit resolution at 100 MHz with RMS error 10 ps (0.36°) resulting in system EVM −29.21 dB with 64-QAM OFDM signals, and the performance can meet the requirements specified in IEEE 802.11a. This work is implemented in a 90nm CMOS process. With the voltage scaling scheme to specific power domains and the low-complexity DCPS design, the overall SCS consumes 850.51 µW from 0.5 V and 1.0 V supplies.