Jui-an Yu

A 0.5 V 4.85 Mbps Dual-Mode Baseband Transceiver With Extended Frequency Calibration for Biotelemetry Applications

This work provides a dual-mode baseband transceiver chipset for wireless body area network (WBAN) system. The modulation schemes include multi-tone code division multiple access (MT-CDMA) and orthogonal frequency division multiplexing (OFDM) to meet multi-user coexistence (up to 8) and high data rate purposes. Based on the analysis of the WBAN operation behavior, several methods including higher data rate, optimal storage determination, and low power implementation techniques are proposed to reduce the transmission energy. To achieve tiny area integration, an embedded phase frequency tunable clock generator and frequency error pre-calibration scheme are provided to extend the frequency mismatch tolerance to 100 ppm (2.5 x of state-of-the-art systems). This chipset is manufactured in 90 nm standard CMOS process. Working at supply voltage of 0.5 V, this chipset is able to provide maximum date rate of 4.85 Mbps with modulator power consumption of 5.52 muW.

A novel technique for I/Q imbalance and CFO compensation in OFDM systems

In this paper, a novel baseband IQ estimation and compensation technique is proposed to overcome the joint effects of CFO (carrier frequency offset) and IQ imbalance. The proposed method uses a one-shot algorithm which is able to estimate and compensate the non-ideal effect up to a gain error of 1 dB, phase error of 10/spl deg/, and CFO of 50 ppm at a carrier frequency of 2.5 GHz in 64QAM OFDM systems. Under this condition, the system performance has less than 0.8 dB design loss in terms of PER and is shown to have more than 10 dB improvement compared with the reference design.

A MT-CDMA based wireless body area network for ubiquitous healthcare monitoring

This paper presents a multi-tone CDMA (MT-CDMA) based system specification for wireless body area network (WBAN) applications. According to the factors of bandwidth, carrier frequency, and electric field intensity defined in wireless medical telemetry service, the function blocks and data format are designed through the considerations of hardware cost, power consumption, and system performance. The design constraints for baseband processor, data conversion, and RF circuits are defined. This work achieves PER=1% and allows interferer distance less than 1.01 m. In energy-spectrum efficiency, it provides 3.125 times energy-spectrum product less than the state-of-the-art systems for healthcare applications.

Estimation of Carrier Frequency Offset With I/Q Mismatch Using Pseudo-Offset Injection in OFDM Systems

This work presents a novel carrier frequency offset (CFO) estimation algorithm, based on pseudo-CFO (P-CFO), to estimate the CFO value under the conditions of I/Q mismatch for direct conversion structures with 2-dB gain error and 20-deg. phase error in frequency selective fading channels. To circumvent CFO with I/Q mismatch, the proposed P-CFO algorithm rotates three training symbols by adding extra frequency offset into the received sequence to improve CFO estimation. Simulation results indicate that the estimation error of the proposed method is about 0.3 ppm, which is lower than those of two-repeat preamble-based methods. Additionally, the proposed P-CFO algorithm is compatible with the conventional method, and is appropriate for SoC implementation. The proposed scheme is implemented as part of an orthogonal frequency-division multiplexing wireless receiver fabricated in a 0.13-mum CMOS process with 3.3 times 0.4 mm2 core area and 10-mW power consumption at 54-Mbits/s data rate.

A Low Voltage All-Digital On-Chip Oscillator Using Relative Reference Modeling

This paper presents a low voltage on-chip oscillator which can compensate process, voltage, and temperature (PVT) variation in an all-digital manner. The relative reference modeling applies a pair of ring oscillators as relative references and estimates period of the internal ring oscillator. The period estimation is parameterized by a second-order polynomial. Accordingly, the oscillator compensates frequency variations in a frequency division fashion. A 1-20 MHz adjustable oscillator is implemented in a 90-nm CMOS technology with 0.04 mm area. The fabricated chips are robust to variations of supply voltage from 0.9 to 1.1 V and temperature range from 0°C to 75°C. The low supply voltage and the small area make it suitable for low-cost and low-power systems.

A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters

Linear amplification with nonlinear components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital signal component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06 mm2. The DCPS can generate phase-modulated signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34°). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 μW which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15° phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10° phase mismatch, the system EVM of - 29.81 dB and ACPR of - 34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM signals.

A frequency accuracy enhanced sub-10µW on-chip clock generator for energy efficient crystal-less wireless biotelemetry applications

A frequency accuracy enhanced clock generator is proposed for energy efficient crystal-less WBAN system. By applying a self-reference calibration and tracking a remote downlink wireless reference, the robust system clock with ±30ppm accuracy against both 20% voltage variation and 75°C temperature variation is developed to enable over-Mbps uplink data transmission. Furthermore, the clock generator based on hysteresis delay cells consumes 7.6µW in 5MHz and is able to minimize significant always-on clock source power.

A Sub-10-

This brief presents an all digitally controlled oscillator (DCO) design with two newly proposed hysteresis delay cells (HDCs) for wireless body area network applications. According to circuit topologies, the two HDCs are defined as on-off and cascaded HDCs that provide various propagation delay values. These HDCs form a simple oscillator structure based on a power-of-2 delay stage DCO (P2-DCO) architecture. Each delay stage provides half of the delay of the previous delay stage in descending order, enabling low-power and small-area features. The P2-DCO is verified in a 90-nm CMOS technology for wide operating frequencies with area of 80 μm X 80 μm and least significant bit resolution of 2.05 ps. With a supply voltage of 1.0 V, the measured dynamic power values are 5.4 and 166 μW at 3.4 and 163.2 MHz, respectively.

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This paper reports an embedded crystal (eCrystal) oscillator which is capable of compensating process, voltage, and temperature (PVT) variation. The delay behaviors of two different delay cells are exploited for the delay estimation. Then the estimated delay is parameterized by a second order approximated function. According to the estimated delay, the eCrystal oscillator is able to calibrate the frequency error without any external reference. A 40MHz oscillator is implemented in a 90-nm CMOS technology with area of 0.4mm2 by an all-digital approach. The fabricated chip is measured under supply voltage from 0.9V to 1.1V and temperature range from 0°C to 75°C with active power consumption of 237µW.

Digitally Controlled Oscillator Based on Hysteresis Delay Cell Topologies for WBAN Applications

A synchronization method includes packet detection and frequency error estimation (PAFEE) is proposed for crystalless OFDM-based wireless body area network (WBAN) applications to enlarge the frequency error tolerance between the transmitter and receiver. The packet detection method is designed to overcome the large frequency error. The estimated frequency offset (FO) value is provided to a crystal-less tunable clock source. The evaluation platform is the eCrystal WiBoC OFDM-based system. The system overall frequency error tolerance is extended 140x of existing wireless systems. The system is designed and simulated in a 90nm technology with 148.5µW computation power and 0.06mm2 area overhead. Comparing to quartz crystal systems, the overall power reduction is 89.3%, and area reduction is 98.4%.