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Featured researches published by Tse-yun Feng.


IEEE Transactions on Computers | 1994

A new routing algorithm for a class of rearrangeable networks

Tse-yun Feng

This paper presents a routing algorithm for a class of multistage interconnection networks. Specifically, the concatenation of two Omega networks which has 2 log/sub 2/ N stages is treated. It is shown that this kind of asymmetric Omega+Omega network can be converted into a symmetric Omega/sup -1spl times/Omega network or a symmetric Omega/spl times/Omega/sup -1/ network. However, they have butterfly connections between the two center stages. A general algorithm is developed which routes a class of symmetric networks. The algorithm routes the network from center stages to outer stages at both the input and the output sides simultaneously. The algorithm presented is simpler and more flexible than the well-known looping algorithm in that it can be applied adaptively according to the structure of the network. It can be applied to routing the Omega-based networks regardless of the center-stage connection patterns, i.e., straight, skewed straight, simple butterfly or skewed butterfly as long as the networks are symmetric. The sufficient conditions for proper routing are shown and proved. In addition, an example is shown to demonstrate the algorithm. >


IEEE Transactions on Reliability | 1989

Reliability evaluation of hypercube multicomputers

Jong Kim; Chita R. Das; Woei Lin; Tse-yun Feng

An analytic model for the reliability evaluation of hypercube multicomputers is presented. The model is based on the decomposition principle, where a hypercube of a higher dimension is recursively decomposed into smaller hypercubes, until the reliability of the smallest cube is modeled exactly. The reliability of the large n-cube is then obtained from this smallest base model using a recursive equation. The reliability model used is task-based, i.e., it is assumed that the system is operational if a task can be executed on the system. Analytic results are given for n-dimensional hypercubes with up to 75% system degradation. The model is validated by comparison of analytic results with simulation results. >


IEEE Transactions on Parallel and Distributed Systems | 1995

The composite banyan network

Tse-yun Feng

A new multipath multistage interconnection network called the composite banyan network is proposed. The network incorporates both the banyan and the reverse banyan networks and is constructed by superimposing the two. The basic building blocks in the composite banyan network are 3/spl times/3 switching elements with log/sub 2/N stages. A major advantage of the composite banyan network over existing networks with 3/spl times/3 SEs is an efficient and fast control algorithm that sets up a path between any source and destination pair. Instead of complex numerical calculations, the network can easily generate a primary routing tag and alternate tags through simple binary operations. Also, the network has a lot of favorable features, including regularity, symmetry, and easy rerouting capability under faults and conflicts. It is shown that at least two totally disjoint paths exist between any source and destination pair, which increase the degree of fault-tolerance. A deterministic permutation routing algorithm is also developed for the 8/spl times/8 composite banyan network, Using a simple tabular method, it is shown that the algorithm always finds a set of conflict-free tags. >


IEEE Transactions on Parallel and Distributed Systems | 1999

Permutation realizability and fault tolerance property of the inside-out routing algorithm

Tse-yun Feng; Hyoung-Il Lee

In this paper, we analyze ways of realizing permutations in a class of 2log/sub 2/N- or (2log/sub 2/N-1)-stage rearrangeable networks. The analysis is based on the newly developed inside-out routing algorithm and we derive the upper and lower bounds on the number of possible realizations of a permutation. It is shown that the algorithm can provide us with comparable degrees of freedom in realizing a given permutation as the well-known looping algorithm, while it can be more generally applied to a class of 2log/sub 2/N- or (2log/sub 2/N-1)-stage rearrangeable networks. In finding a set of complete assignments for the center-stage cycles, alternate realizations of a permutation can be obtained by changing the initial position, changing the assigning direction, or even interchanging the first-level decompositions of the permutation. We also show that these numerable alternate realizations can be utilized to make the networks tolerate some sets of faults, i.e., control faults of SEs including stuck-at-straight and stuck-at-cross. Various cases of single control faults at the center stages and other stages are examined through examples. These new approaches originate from routing outward from center stages to outer stages; therefore, the center stages and two half networks may be treated separately.


IEEE Transactions on Computers | 1994

Performance analysis of cluster-based multiprocessors

Prasant Mohapatra; Chita R. Das; Tse-yun Feng

A queueing model for performance evaluation of cluster-based multiprocessors is proposed. Most system components are modeled as M/D/1/L queues to capture deterministic service time and finite buffer behavior. Various subsystems are analyzed independently and then integrated for the system level analysis. Average delay, throughput, and processor utilization are the performance parameters studied in this analysis. The analytical results are first validated via simulation. Next, several design alternatives are discussed using the model. These include the effect of buffer length and identification of bottleneck centers for various design configurations. >


international workshop on variable structure systems | 1988

Fast data selection and broadcast on the Butterfly network

Woei Lin; Tsang-Ling Sheu; Chita R. Das; Tse-yun Feng; Chuan-lin Wu

A quadtree communication structure is presented, along with two associated procedures for efficient, contention-free data selection and broadcast on the BBN Butterfly parallel processor and its family. the proposed structure suggests a general approach to mapping a class of parallel algorithms with intensive communication requirements for performing two primitive operations: selecting data from many different sources and distributing data from a single source. While performing these two operations through the quadtree structure, the two procedures, ascend and descend, incur no link conflicts in the Butterfly network. By properly merging messages and efficiently replicating data, they can complete required communications in O(log/sub 4/ M) parallel steps, where M is the size of a Butterfly parallel processor. Contraction and stretch of the quadtree communication structure while retaining the conflict-free property, is considered. The contracted and stretched tree structures allow the adaptive balance of computations and communication requirements for various algorithms with different computation/communication ratios.<<ETX>>


IEEE Transactions on Computers | 1989

A conflict-free routing scheme on multistage interconnection networks

Woei Lin; Tsang-Ling Sheu; Chita R. Das; Tse-yun Feng; Chuan-lin Wu

A conflict-free routing scheme is presented for a class of parallel and distributed computing systems. The core of the scheme is a quadtree communication structure. The quadtree structure suggests a general approach to mapping a class of parallel algorithms with intensive communication requirements for selecting data from many different sources and distributing data from a single source. By properly merging messages and efficiently replicating data, the quadtree structure can complete required communications in O(log/sub 4/ M) parallel steps, where M is the network size. It is shown that the size of a quadtree communication structure can be contracted and stretched by adjusting the number of descendent nodes without affecting its conflict-free property. The relationship between the computation/communication ratio of various parallel algorithms and the number of tree levels is presented, and finally, their joint effect on the response time of combining and distributing data messages is examined. This analysis helps determine the optimal adaptation of the quadtree for minimizing the overall algorithm execution time. >


midwest symposium on circuits and systems | 1993

A simulation scheme in rearrangeable networks

Tse-yun Feng; Yanggon Kim

In this paper, we present a new simulation scheme for verifying the rearrangeability of the 2log/sub 2/N- or (2log/sub 2/N-1)-stage networks. Instead of the exhaustive method which is actually impossible due to the prohibitively large amount of cases, the proposed scheme simulates just for the representative cases for the possible permutations. First of all, a cyclic characteristic of the center stages in the network is discussed. From the graph theoretical point of view, we show that any permutation can be decomposed into two subpermutations and in addition, show that each subpermutation can be divided further into groups called loops so that they can match the center-stage cycles. By using these two concepts, it is shown that any possible permutation for N=16 falls into one of the categories and is proved that all of them can be realized without conflict on the network.<<ETX>>


ieee computer society workshop on future trends of distributed computing systems | 2001

Multifunctional optical switches for multistage interconnection networks

Zhenshan Zhang; Tse-yun Feng

Two designs of optical switching elements for multistage interconnection networks are proposed based on the polarization of light beams. The optical switching elements can perform not only conventional go-straight and crossover switching but also upper and lower broadcasting. The first switch comprises polarizers, polarizing beam combiners, magneto-optic rotators, and polarizing beam splitters. The second switch utilizes polarization-selective birefringence holograms as beam splitters and lead lanthanum zirconated titanate as polarization rotators. The switch was integrated onto a silicon substrate with a planar configuration. A large multistage interconnection network can be built through a cascade of the 2/spl times/2 switching elements using either design.


ieee international conference on high performance computing data and analytics | 1998

The Augmented Composite Banyan Network

Hyoung-Il Lee; Tse-yun Feng

A new multipath multistage interconnection network called the Augmented Composite Banyan Network (ACBN) is proposed. The ACBN is created by adding a link to each SE of the Composite Banyan Network (CBN), which is a multipath network with at least two disjoint paths and was originally proposed in (Seo and Feng, 1995). Therefore, the basic building blocks in the ACBN are 4/spl times/4 SEs with log/sub 2/N stages. The ACBN inherits the favorable features of the CBN such as regularity, symmetry and easy rerouting capability under faults and conflicts. The ACBN also has an efficient and fast control algorithm that can easily generate a primary routing tag and alternative routing tags as in the CBN. A major improvement of the ACBN over the CBN is the higher connectivity with four disjoint paths between any source and destination pair. Moreover the ACBN can generate alternative routing tags in a much simpler way i.e., by a simple binary operation not by the conversion table as in the CBN. To compare the ACBN with other networks in connectivity, we introduce the definition of a degree of connectivity as a new connectivity measure function. The comparison results show that due to high connectivity the ACBN can resolve more random connection requests than other networks by using only a small amount of additional hardware.

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Yanggon Kim

Pennsylvania State University

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Chita R. Das

Pennsylvania State University

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Woei Lin

Pennsylvania State University

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Chuan-lin Wu

University of Texas at Austin

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Hyoung-Il Lee

Seoul National University

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Jong Kim

Pennsylvania State University

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Zhenshan Zhang

Pennsylvania State University

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