Tsubasa Matsumoto

Anisotropic diamond etching through thermochemical reaction between Ni and diamond in high-temperature water vapour

Diamond possesses excellent physical and electronic properties, and thus various applications that use diamond are under development. Additionally, the control of diamond geometry by etching technique is essential for such applications. However, conventional wet processes used for etching other materials are ineffective for diamond. Moreover, plasma processes currently employed for diamond etching are not selective, and plasma-induced damage to diamond deteriorates the device-performances. Here, we report a non-plasma etching process for single crystal diamond using thermochemical reaction between Ni and diamond in high-temperature water vapour. Diamond under Ni films was selectively etched, with no etching at other locations. A diamond-etching rate of approximately 8.7 μm/min (1000 °C) was successfully achieved. To the best of our knowledge, this rate is considerably greater than those reported so far for other diamond-etching processes, including plasma processes. The anisotropy observed for this diamond etching was considerably similar to that observed for Si etching using KOH.

B-doped diamond field-effect transistor with ferroelectric vinylidene fluoride–trifluoroethylene gate insulator

A B-doped diamond field-effect transistor (FET) with a ferroelectric vinylidene fluoride–trifluoroethylene (VDF–TrFE) copolymer gate insulator was fabricated. The VDF–TrFE film deposited on the B-doped diamond showed good insulating and ferroelectric properties. Also, a Pt/VDF–TrFE/B-doped diamond layered structure showed ideal behavior as a metal–ferroelectric–semiconductor (MFS) capacitor, and the memory window width was 11 V, when the gate voltage was swept from 20 to −20 V. The fabricated MFS-type FET structure showed the typical properties of a depletion-type p-channel FET and a maximum drain current density of 0.87 mA/mm at room temperature. The drain current versus gate voltage curves of the proposed FET showed a clockwise hysteresis loop owing to the ferroelectricity of the VDF–TrFE gate insulator. In addition, we demonstrated the logic inverter with the MFS-type diamond FET coupled with a load resistor, and obtained the inversion behavior of the input signal and a maximum gain of 18.4 for the present circuit.