Norio Tokuda

Inversion channel diamond metal-oxide-semiconductor field-effect transistor with normally off characteristics.

We fabricated inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off characteristics. At present, Si MOSFETs and insulated gate bipolar transistors (IGBTs) with inversion channels are widely used because of their high controllability of electric power and high tolerance. Although a diamond semiconductor is considered to be a material with a strong potential for application in next-generation power devices, diamond MOSFETs with an inversion channel have not yet been reported. We precisely controlled the MOS interface for diamond by wet annealing and fabricated p-channel and planar-type MOSFETs with phosphorus-doped n-type body on diamond (111) substrate. The gate oxide of Al2O3 was deposited onto the n-type diamond body by atomic layer deposition at 300u2009°C. The drain current was controlled by the negative gate voltage, indicating that an inversion channel with a p-type character was formed at a high-quality n-type diamond body/Al2O3 interface. The maximum drain current density and the field-effect mobility of a diamond MOSFET with a gate electrode length of 5u2009μm were 1.6u2009mA/mm and 8.0u2009cm2/Vs, respectively, at room temperature.

Nonuniformity in Ultrathin SiO2 on Si(111) Characterized by Conductive Atomic Force Microscopy

We have investigated two-dimensional fluctuation of current through 1.1-nm-thick SiO2 film using a conductive atomic force microscope. Upon analysis of the correlation between current and oxide surface morphology, the current was found to be larger at the low points in the topography. The correlation coefficient was varied in the measured areas. In addition, the current fluctuation correlated well with the topographical height using the direct tunneling formula in the high correlation area, from which we concluded that the oxide film shows nonuniform thickness as reflected by the surface morphology.

Topography Change Due to Multilayer Oxidation at SiO2/Si(111) Interfaces

Using a Si(111) surface with atomistically flat wide terraces, topography change of the SiO2/Si interfaces during thermal oxidation was investigated by means of atomic force microscopy. We observed vestiges of oxidation at the interfaces of SiO2 films with various thicknesses at three different temperatures. We found that the SiO2/Si interface consisted of at least three layers over the entire range of our experiments. This result indicates that layer-by-layer oxidation does not progress at the SiO2/Si interfaces strictly. The densities of vestiges get increased as the oxidation temperature decreased. This topographic change arises from the different temperature dependence between two oxidation rates in parallel and perpendicular to the SiO2/Si interface.

Leakage Current Distribution of Cu-Contaminated Thin SiO2

Dielectric degradation of an intentionally Cu-contaminated SiO2 film on an Si substrate was investigated using conducting atomic force microscopy. It was shown that local oxide leakage current did not increase at points occupied by Cu particles, while it increased at points other than that occupied by Cu particles. Combination of sulfuric acid/hydrogen peroxide mixture immersion and total reflection X-ray fluorescence analyses indicated that high-density Cu atoms near the SiO2 surface induced the high leakage current.

Selective Growth of Monoatomic Cu Rows at Step Edges on Si(111) Substrates in Ultralow-Dissolved-Oxygen Water

We have fabricated high-aspect-ratio monoatomic Cu rows along atomic step edges on vicinal Si(111) substrates. The method consists of two wet processes: (1) the formation of a step/terrace structure by immersing a Si(111) substrate in ultralow-dissolved-oxygen water (LOW) and (2) the formation of the nanowires by immersion in LOW containing Cu ions. A systematic investigation of Si(111) surfaces with the nanowire has been performed by means of atomic force microscopy, Fourier-transform infrared absorption spectroscopy, and total-reflection X-ray fluorescence spectroscopy.

Selective Growth of Cu Nanowires on Si(111) Substrates

We succeeded in the fabrication of high-aspect-ratio (length to width) Cu nanowires of less than 10 nm width and 0.5 nm height along atomic step edge lines on Si(111) substrate. The fabrication procedure consisted of two wet process steps: (1) flattening of the surface roughness to an atomic level by immersing Si(111) wafers in ultralow-dissolved-oxygen water (LOW) and (2) Cu nanowire formation by immersion in LOW containing 100 ppb Cu ions for 100 s at room temperature. The selective growth of the Cu nanowires at the step edges indicates that Cu adsorption sites could be formed there during the flattening stage.

SiO2 Surface and SiO2/Si Interface Topography Change by Thermal Oxidation

Using a wide atomically flat (111) Si surface, the topography change of SiO2 surface and SiO2/Si interface by thermal oxidation was investigated for various oxidation temperatures. The initial step/terrace configuration was preserved on the SiO2 surface irrespective of oxidation temperature. On the other hand, the general step/terrace configuration of the initial Si surface was succeeded by the SiO2/Si interface at temperatures lower than 950°C, while at temperatures higher than 1050°C, the configuration was destroyed at the SiO2/Si interface with increasing oxide thickness until the steps finally disappeared. Terrace surfaces, however, were steeply microscopically roughened in the initial oxidation range irrespective of the oxidation temperature.

Atomic topography change of SiO2/Si interfaces during thermal oxidation

Using an Si(111) surface with atomically flat, wide terraces, the topographic change of SiO2/Si interfaces during thermal oxidation was investigated at an oxidation temperature of 1050°C using an atomic force microscope. Vestiges of two-dimensional oxide-island growth were observed at the interface. Then, a histogram for roughness height distribution based on atomic force microscope (AFM) data was plotted in order to evaluate the roughness within the terraces at the interface instead of the root mean square (RMS). This method revealed that the SiO2/Si interface consists of at least three layers separated from one another by 0.3 nm. This result provides evidence of the layer-by-layer model breaking down at the SiO2/Si interfaces.

Effect of SiO2 Fence on Atomic Step Flow in Chemical Etching of Si Surface

A method of realizing Si surfaces without step lines in predetermined areas surrounded by SiO2 fences was investigated. The SiO2 fence blocked the atomic step flow during chemical etching of the Si surface. Atomic step flow in the downside of the SiO2 fences stopped at the SiO2 fences, while atomic step flow in the upside of the SiO2 fences during the chemical etching of the Si surface was able to progress. This technique is applicable to the fabrication of nanodevices in any predetermined area isolated with SiO2 regions.

H-terminated diamond field effect transistor with ferroelectric gate insulator

An H-terminated diamond field-effect-transistor (FET) with a ferroelectric vinylidene fluoride (VDF)-trifluoroethylene (TrFE) copolymer gate insulator was fabricated. The VDF-TrFE film was deposited on the H-terminated diamond by the spin-coating method and low-temperature annealing was performed to suppress processing damage to the H-terminated diamond surface channel layer. The fabricated FET structure showed the typical properties of depletion-type p-channel FET and showed clear saturation of the drain current with a maximum value of 50u2009mA/mm. The drain current versus gate voltage curves of the proposed FET showed clockwise hysteresis loops due to the ferroelectricity of the VDF-TrFE gate insulator, and the memory window width was 19u2009V, when the gate voltage was swept from 20 to −20u2009V. The maximum on/off current ratio and the linear mobility were 108 and 398u2009cm2/Vu2009s, respectively. In addition, we modulated the drain current of the fabricated FET structure via the remnant polarization of the VDF-TrFE ga...