Network


Latest external collaboration on country level. Dive into details by clicking on the dots.

Hotspot


Dive into the research topics where Tsun-Hsien Wang is active.

Publication


Featured researches published by Tsun-Hsien Wang.


IEEE Transactions on Multimedia | 2015

Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment

Tsun-Hsien Wang; Cheng-Wen Chiu; Wei-Chen Wu; Jen-Wen Wang; Chun-Yi Lin; Ching-Te Chiu; Jing-Jia Liou

New generations of display technologies provide a significantly improved dynamic range compared to conventional display devices. Inverse tone mapping methods have been proposed to convert low dynamic range (LDR) images to HDR ones, and several of them require multiple exposure LDR images of the same scene as inputs. However, the vast majority of LDR images and videos available have only one single exposure. In this paper, we propose a region-based enhancement of the pseudo-exposures to generate an HDR image. First, we present an exposure dependent curve to convert one LDR image to the pseudo-multiple-exposures. Only certain regions of the pseudo-exposures contain noticeable detail information. We propose a region-based enhancement on the pseudo-exposures to boost details in the most distinct region. Thereby the region-enhanced pseudo-exposures are fused into an HDR image. The fused image thus enhances details in the bright region of the dark image and the dark region of the bright image. Compared with other inverse tone mapped methods, our method generates lower total contrast error measured under the dynamic range independent image quality assessment method in [1].


international conference on image processing | 2007

Design and Implementation of a Real-Time Global Tone Mapping Processor for High Dynamic Range Video

Tsun-Hsien Wang; Wei-Su Wong; Fang-Chu Chen; Ching-Te Chiu

As the development in high dynamic range (HDR) video capture technologies, the bit-depth video encoding and decoding has become an interesting topic. In this paper, we show that the real-time HDR video display is possible. A tone mapping based HDR video architecture pipelined with a video CODEC is presented. The HDR video is compressed by the tone mapping processor. The compressed HDR video can be encoded and decoded by the video standards, such as MPEG2, MPEG4 or H.264 for transmission and display. We propose and implement a modified photographic tone mapping algorithm for the tone mapping processor. The required luminance wordlength in the processor is analyzed and the quantization error is estimated. We also develop the digit-by-digit exponent and logarithm hardware architecture for the tone mapping processor. The synthesized results show that our real-time tone mapping processor can process a NTSC video with 720*480 resolution at 30 frames per second.


international conference on image processing | 2011

Low visual difference virtual high dynamic range image synthesizer from a single legacy image

Tsun-Hsien Wang; Ching-Te Chiu

New generations of display technologies provide signicantly improved dynamic range over conventional display devices. Current inverse tone mapping schemes require multiple exposure low dynamic range (LDR) images to generate high dynamic range (HDR) images. In this work, we propose an exposure dependent S curve to convert one optimized LDR image to multiple images with different brightness, which are then fused into a virtual real scene HDR image with wide dynamic range. According to our implementation results, the dynamic range can reach about 105. The synthesizer is robust and temporally coherent, and does not require image specific parameter adjustment. This paper also presents the image quality assessment with HDR visual difference predictor (HDR-VDP) and relative entropy contrast, and our work has better performance than other inverse tone mapping operators (iTMOs) for the both image quality assessments.


international conference on image processing | 2007

Block-Based Gradient Domain High Dynamic Range Compression Design for Real-Time Applications

Tsun-Hsien Wang; Wei-Ming Ke; Ding-Chuang Zwao; Fang-Chu Chen; Ching-Te Chiu

Due to progress in high dynamic range (HDR) capture technologies, the HDR image or video display on conventional LCD devices has become an important topic. Many tone mapping algorithms are proposed for rendering HDR images on conventional displays, but intensive computation time makes them impractical for video applications. In this paper, we present a real-time block-based gradient domain HDR compression for image or video applications. The gradient domain HDR compression is selected as our tone mapping scheme for its ability to compress and preserve details. We divide one HDR image/frame into several equal blocks and process each by the modified gradient domain HDR compression. The gradients of smaller magnitudes are attenuated less in each block to maintain local contrast and thus expose details. By solving the Poisson equation on the attenuated gradient field block by block, we are able to reconstruct a low dynamic range image. A real-time Discrete Sine Transform (DST) architecture is proposed and developed to solve the Poisson equation. Our synthesis results show that our DST Poisson solver can run at 50 MHz clock and consume area of 9 mm2 under TSMC 0.18 um technology.


international conference on multimedia and expo | 2007

Low Power Design of High Performance Memory Access Architecture for HDTV Decoder

Tsun-Hsien Wang; Ching-Te Chiu

To improve memory access efficiency and to reduce power consumption in HDTV video decoders, we propose a novel memory address mapping method and an efficient memory accessing architecture. The memory address mapping enables a computation-free memory address generation from the logical address of the data word in a video frame. The simple address generation is achieved by combining neighboring macroblocks into groups and stores the group of macroblocks in the same row of the external memory. By grouping suitable macroblocks, depending on interlaced or progressive scanning, we significantly reduce the cross-row memory accessing in the external memory, which is both time consuming and power consuming. In the memory accessing architecture, we rearrange the access order of luminance and chrominance data in motion compensations to further reduce the number of row changes of the external memory. Our analysis shows that the number of row changes is reduced by 87.67% and throughput of our memory-accessing scheme is improved by 30.91% compared to conventional approaches.


international conference on image processing | 2009

Hardware-efficient virtual high dynamic range image reproduction

Wei-Ming Ke; Tsun-Hsien Wang; Ching-Te Chiu

High dynamic range (HDR) images keep dynamic range of luminance from 105 to 108 and preserve more details than low dynamic range (LDR) images. Conventional acquisition of HDR images requires several images with different exposure settings of one scene, so multiple cameras or static scene are necessary. Besides, in order to transform HDR images onto normal LDR display, tone-mapping algorithms are required which need intensive computations. In this paper, we propose a hardware-efficient virtual HDR image synthesizer that includes virtual photography and local contrast enhancement. Only one LDR image is enough to generate HDR-like images, with fine details and uniformly-distributed intensity. A real-time hardware display system suitable for image or video contrast enhancement is also implemented. Under UMC90nm technology, we can process video sequences with NTSC 720ç480 resolution at 60 frames per second (FPS), running at 100MHz and consume 0.3mm2 silicon area.


signal processing systems | 2013

Edge curve scaling and smoothing with cubic spline interpolation for image upscaling

Wei-Chen Wu; Tsun-Hsien Wang; Ching-Te Chiu

Image up-scaling is an important technique to increase the resolution of an image. Earlier interpolation based approaches have low computation complexity while cause blurring and ringing artifacts in edge regions due to the loss of high frequency details. Patch-based super resolution achieves satisfactory up-scaling images at the penalty of high computation cost. In this paper, we present a scalable edge map to recover high frequency components of edge regions in up-scaled images to improve the sharpness and use a range compression method to reduce ringing artifacts. We propose an efficient 1-D and 2-D approaches to extract edge curves from an original image. Then the cubic spline interpolation is adopted to up-scale an edge map. A smooth function is added to remove zigzag, stair, trapezoid artifacts. Then we apply the patch-based method only on up-scaled edge map to recover the high frequency components. The execution time of our proposed method is only 10 % to 5 % compared to the multi-resolution patch-based super resolution method. Experimental results show that we can achieve similar image quality with G. Freedman et al.’s method [19].


international conference on image processing | 2008

Design optimization of a global/local tone mapping processor on arm SOC platform for real-time high dynamic range video

Ching-Te Chiu; Tsun-Hsien Wang; Wei-Ming Ke; Chen-Yu Chuang; Jhih-Rong Chen; Rong Yang; Ren-Song Tsay

As the advance of high quality displays such as organic light- emitting diode (OLED) or laser TV, the importance of a real-time high dynamic range (HDR) data processing for display devices increases significantly. Many tone mapping algorithms are proposed for rendering HDR images or videos on display screens. The choice of tone mapping algorithm depends on characteristics of displays such as luminance range, contrast ratio and gamma correction. An ideal HDR tone mapping processor should include several tone mapping algorithms and be able to select an appropriate one for different kind of devices and applications. Such a HDR tone mapping processor has characteristics of robust core functionality, high flexibility, and low area consumption. An ARM core based system on chip (SOC) platform with HDR tone mapping ASIC is suitable for such applications. In this paper, we present a systematic methodology to develop an optimized architecture for tone mapping processor in the ARM SOC platform. We illustrate the approach by a HDR tone mapping processor that can handle both photographic and gradient compression. The optimization is achieved through four major steps: common module extraction, computation power enhancement, hardware/software partition and cost function analysis. Based on the proposed scheme, we develop an integrated photographic and gradient compression HDR tone mapping processor that can process 1024times768 images at 60 fps. This design runs at 100 MHz clock and consumes area of 13.8 mm2 under TSMC 0.13 mum technology with 50% improvement in speed and area compared with previous results.


signal processing systems | 2008

A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 μm technology

Ching-Te Chiu; Tsun-Hsien Wang; Wei-Ming Ke; Chen-Yu Chuang; Jhih-Siao Huang; Wei-Su Wong; Ren-Song Tsay

As the advance of high quality displays such as light-emitting diode (LED), liquid-crystal-display (LCD) or laser TV, the importance of a real-time high dynamic range (HDR) data processing for display devices increases significantly. Many tone mapping algorithms are proposed for rendering HDR images or videos on display screens. The choice of tone mapping algorithm depends on characteristics of displays such as luminance range, contrast ratio and gamma correction. An ideal HDR tone mapping processor should include different types of tone mapping algorithms and be able to select an appropriate one depending on devices and applications. The photographic tone reproduction has lower complexity and better quality among global tone mapping schemes. The gradient compression, a local tone mapping, is known for detail preservation. In this paper, we present an integrated photographic and gradient tone mapping processor that can be configured for different applications. This design that can process 1024 times 768 images at 60 fps runs at 100 MHz clock and consumes core area of 8.1 mm2 under TSMC 0.13 mum technology with 50% improvement in speed and area compared with previous results.


international conference on image processing | 2013

Edge curve scaling and smoothing with cubic spline interpolation

Wei-Chen Wu; Tsun-Hsien Wang; Ching-Te Chiu

Image scaling is a widely used method for many applications and numerous approaches have been proposed to this issue. Current approaches that bring promising results while the edge curves of the scaled up image still have blurring effect. This paper focuses on the edge curve of an image. We propose a simple method for edge curve scaling to avoid the disconnect and zigzag problems when using cubic spline interpolation. The scaling results of our method can avoid blurring of the edge curve and maintain the edge contour of an input image.

Collaboration


Dive into the Tsun-Hsien Wang's collaboration.

Top Co-Authors

Avatar

Ching-Te Chiu

National Tsing Hua University

View shared research outputs
Top Co-Authors

Avatar

Wei-Ming Ke

National Tsing Hua University

View shared research outputs
Top Co-Authors

Avatar

Chen-Yu Chuang

National Tsing Hua University

View shared research outputs
Top Co-Authors

Avatar

Ren-Song Tsay

National Tsing Hua University

View shared research outputs
Top Co-Authors

Avatar

Wei-Chen Wu

National Tsing Hua University

View shared research outputs
Top Co-Authors

Avatar

Wei-Su Wong

National Tsing Hua University

View shared research outputs
Top Co-Authors

Avatar

Fang-Chu Chen

Industrial Technology Research Institute

View shared research outputs
Top Co-Authors

Avatar

Jhih-Siao Huang

National Tsing Hua University

View shared research outputs
Top Co-Authors

Avatar

Cheng-Wen Chiu

National Tsing Hua University

View shared research outputs
Top Co-Authors

Avatar

Chun-Yi Lin

National Tsing Hua University

View shared research outputs
Researchain Logo
Decentralizing Knowledge