Ching-Te Chiu

Switching Bilateral Filter With a Texture/Noise Detector for Universal Noise Removal

In this paper, we propose a switching bilateral filter (SBF) with a texture and noise detector for universal noise removal. Operation was carried out in two stages: detection followed by filtering. For detection, we propose the sorted quadrant median vector (SQMV) scheme, which includes important features such as edge or texture information. This information is utilized to allocate a reference median from SQMV, which is in turn compared with a current pixel to classify it as impulse noise, Gaussian noise, or noise-free. The SBF removes both Gaussian and impulse noise without adding another weighting function. The range filter inside the bilateral filter switches between the Gaussian and impulse modes depending upon the noise classification result. Simulation results show that our noise detector has a high noise detection rate as well as a high classification rate for salt-and-pepper, uniform impulse noise and mixed impulse noise. Unlike most other impulse noise filters, the proposed SBF achieves high peak signal-to-noise ratio and great image quality by efficiently removing both types of mixed noise, salt-and-pepper with uniform noise and salt-and-pepper with Gaussian noise. In addition, the computational complexity of SBF is significantly less than that of other mixed noise filters.

Unified parallel lattice structures for time-recursive discrete cosine/sine/Hartley transforms

Unified efficient computations of the discrete cosine transform (DCT), discrete sine transform (DST), discrete Hartley transform (DHT), and their inverse transforms employing the time-recursive approach are considered. Unified parallel lattice structures that can dually generate the DCT and DST simultaneously as well the DHT are developed. These structures can obtain the transformed data for sequential input time recursively with a throughput rate of one per clock cycle. The total number of multipliers required is a linear function of the transform size N, with no constraint on N. The resulting architectures are regular, modular, and without global communication so that they are very suitable for VLSI implementation for high-speed applications. It is shown that the DCT, DST, DHT and their inverse transforms share an almost identical lattice structure. The tradeoff between time and area for the block data processing is considered. >

Optimal unified architectures for the real-time computation of time-recursive discrete sinusoidal transforms

An optimal unified architecture that can efficiently compute the discrete cosine, sine, Hartley, Fourier, lapped orthogonal, and complex lapped transforms for a continuous stream of input data that arise in signal/image communications is proposed. This structure uses only half as many multipliers as the previous best known scheme (Liu and Chiu, 1993). The proposed architecture is regular, modular, and has only local interconnections in both data and control paths. There is no limitation on the transform size N and only 2N-2 multipliers are needed for the DCT. The throughput of this scheme is one input sample per clock cycle. The authors provide a theoretical justification by showing that any discrete transform whose basis functions satisfy the fundamental recurrence formula has a second-order autoregressive structure in its filter realization. They also demonstrate that dual generation transform pairs share the same autoregressive structure. They extend these time-recursive concepts to multi-dimensional transforms. The resulting d-dimensional structures are fully-pipelined and consist of only d 1D transform arrays and shift registers. >

On the design and analysis of fault tolerant NoC architecture using spare routers

The aggressive advent in VLSI manufacturing technology has made dramatic impacts on the dependability of devices and interconnects. In the modern manycore system, mesh based Networks-on-Chip (NoC) is widely adopted as on chip communication infrastructure. It is critical to provide an effective fault tolerance scheme on mesh based NoC. A faulty router or broken link isolates a well functional processing element (PE). Also, a set of faulty routers form faulty regions which may break down the whole design. To address these issues, we propose an innovative router-level fault tolerance scheme with spare routers which is different from the traditional microarchitecture-level approach. The spare routers not only provide redundancies but also diversify connection paths between adjacent routers. To exploit these valuable resources on fault tolerant capabilities, two configuration algorithms are demonstrated. One is shift-and-replace-allocation (SARA) and the other is defect-awareness-path-allocation (DAPA) that takes advantage of path diversity in our architecture. The proposed design is transparent to any routing algorithm since the output topology is consistent to the original mesh. Experimental results show that our scheme has remarkable improvements on fault tolerant metrics including reliability, mean time to failure (MTTF), and yield. In addition, the performance of spare router increases with the growth of NoC size but the relative connection cost decreases at the same time. This rare and valuable characteristic makes our solution suitable for large scale NoC design.

Real-time parallel and fully pipelined two-dimensional DCT lattice structures with application to HDTV systems

The authors propose a fully pipelined architecture to compute the 2D discrete cosine transform (DCT) from a frame-recursive point of view. Based on this approach, two real-time parallel lattice structures for successive frame and block 2D DCT are developed. These structures are fully pipelined with throughput rate N clock cycles for an N*N successive input data frame. Moreover, the resulting 2D DCT architectures are modular, regular, and locally connected and require only two 1D DCT blocks that are extended directly from the 1D DCT structure without transposition. It is therefore suitable for VLSI implementation for high-speed HDTV systems. A parallel 2D DCT architecture and a scanning pattern for HDTV systems to achieve higher performance is proposed. The VLSI implementation of the 2D DCT using distributed arithmetic to increase computational efficiency and reduce round-off error is discussed. >

BiTA/SWCE: Image Enhancement With Bilateral Tone Adjustment and Saliency Weighted Contrast Enhancement

Researchers have proposed various image enhancement methods to make images better correlate to the human visual system. This letter proposed an innovative image enhancement framework that combines bilateral tone adjustment (BiTA) and saliency-weighted contrast enhancement (SWCE) methods. Unlike most curve-based global contrast enhancement methods, BiTA enhances the mid-tone regions that normally contain important scenes, in addition to the bright and dark regions. For local contrast enhancement, SWCE integrates the concept of image saliency into a simple filter-based contrast enhancement method. Regions with higher saliency values, which indicate that the regions have a higher extent of human interest, deserve a greater degree of enhancement. In addition, this letter presents the ratio of saliency-weighted relative entropy to noise to evaluate the enhancement quality. Simulation results show that the proposed schemes achieve high contrast enhancement with little noise and great image quality.

Pseudo-Multiple-Exposure-Based Tone Fusion With Local Region Adjustment

New generations of display technologies provide a significantly improved dynamic range compared to conventional display devices. Inverse tone mapping methods have been proposed to convert low dynamic range (LDR) images to HDR ones, and several of them require multiple exposure LDR images of the same scene as inputs. However, the vast majority of LDR images and videos available have only one single exposure. In this paper, we propose a region-based enhancement of the pseudo-exposures to generate an HDR image. First, we present an exposure dependent curve to convert one LDR image to the pseudo-multiple-exposures. Only certain regions of the pseudo-exposures contain noticeable detail information. We propose a region-based enhancement on the pseudo-exposures to boost details in the most distinct region. Thereby the region-enhanced pseudo-exposures are fused into an HDR image. The fused image thus enhances details in the bright region of the dark image and the dark region of the bright image. Compared with other inverse tone mapped methods, our method generates lower total contrast error measured under the dynamic range independent image quality assessment method in [1].

A 0.64 mm

Face detection is widely used in portable consumer handheld devices aimed at low area, low power, and high performance applications. The boosted cascade algorithm is one of the fastest face detection algorithms in use, but its hardware implementation requires a huge amount of SRAM to store the input data, integral image, and classifiers. This paper proposes a novel cascade face detection architecture based on a reduced two-field feature extraction scheme for faster integral image calculation and feature extraction. This scheme reduces the required memory for storing integral images by 75%, and employs multiple register files instead of a single SRAM to speed up the integral image updating and feature extraction processes. The reduced integral images have only 5% of the features of original images. Although this approach requires more weak classifiers, the proposed parallel cascade detection architecture reduces the average detection time for one feature to 63% that of the original. A 0.64 mm2 15 mw (@390 fps) boosted cascade face detection is implemented under the UMC 90-nm CMOS technology. Experimental results show that this face detection system can achieve a high face detection rate in processing 160 × 120 grayscale images at a speed of 390 fps.

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As the development in high dynamic range (HDR) video capture technologies, the bit-depth video encoding and decoding has become an interesting topic. In this paper, we show that the real-time HDR video display is possible. A tone mapping based HDR video architecture pipelined with a video CODEC is presented. The HDR video is compressed by the tone mapping processor. The compressed HDR video can be encoded and decoded by the video standards, such as MPEG2, MPEG4 or H.264 for transmission and display. We propose and implement a modified photographic tone mapping algorithm for the tone mapping processor. The required luminance wordlength in the processor is analyzed and the quantization error is estimated. We also develop the digit-by-digit exponent and logarithm hardware architecture for the tone mapping processor. The synthesized results show that our real-time tone mapping processor can process a NTSC video with 720*480 resolution at 30 frames per second.

Real-Time Cascade Face Detection Design Based on Reduced Two-Field Extraction

New generations of display technologies provide signicantly improved dynamic range over conventional display devices. Current inverse tone mapping schemes require multiple exposure low dynamic range (LDR) images to generate high dynamic range (HDR) images. In this work, we propose an exposure dependent S curve to convert one optimized LDR image to multiple images with different brightness, which are then fused into a virtual real scene HDR image with wide dynamic range. According to our implementation results, the dynamic range can reach about 105. The synthesizer is robust and temporally coherent, and does not require image specific parameter adjustment. This paper also presents the image quality assessment with HDR visual difference predictor (HDR-VDP) and relative entropy contrast, and our work has better performance than other inverse tone mapping operators (iTMOs) for the both image quality assessments.