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Dive into the research topics where Tsuneo Nakanishi is active.

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Featured researches published by Tsuneo Nakanishi.


international conference on parallel architectures and compilation techniques | 1999

The modulo interval: a simple and practical representation for program analysis

Tsuneo Nakanishi; Akira Fukuda; Kazuki Joe; Constantine D. Polychronopoulos

In this paper, the modulo interval, an extension of the traditional interval on real numbers, and its useful mathematical properties are presented as a representation for program analysis. Only with two additional parameters to the interval on real numbers, namely the modulus and the residue, the modulo interval can represent information on programs having cyclicity such as loop indices, array subscripts etc., at reasonable complexity and more accuracy. Well-defined arithmetic and set operations on the modulo interval make implementation of compilers simple and reliable. Moreover, application of the modulo interval to program analysis for parallelizing compilers is discussed in this paper.


languages and compilers for parallel computing | 1994

The Data Partitioning Graph: Extending Data and Control Dependencies for Data Partitioning

Tsuneo Nakanishi; Kazuki Joe; Akira Fukuda; Keijiro Araki; Hideki Saito; Constantine D. Polychronopoulos

Scalability and cost considerations suggest that distributed and distributed shared memory parallel computers will dominate future parallel architectures. These machines could not be used effectively unless efficient automatic and static solutions to the data partitioning and placement problem become available. Significant progress toward this end has been made in the last few years, but we are still far from having general solutions which are efficient for all classes of applications. In this paper we propose the data partitioning graph (DPG) as an intermediate representation for parallelizing compilers, which augments previous intermediate representations, and provides a framework for carrying out partitioning and placement of not only regular data structures (such as arrays), but also of irregular structures and scalar variables. Although recent approaches to task-graph-based intermediate representations focus on representing data and control dependencies between tasks, they largely ignore the use of program variables by the different tasks. Traditional data partitioning methods usually employ algorithm-dependent techniques, and are considered independently of processor assignments (which ought to be handled simultaneously with data partitioning). Moreover, approaches to data partitioning concentrate exclusively on array structures. By explicitly encapsulating the use of program variables by the task nodes, the DPG provides a framework for handling data partitioning as well as processor assignment in the same context. We also discuss the hierarchical data partitioning graph (HDPG) which encapsulates the hierarchy of the compiled programs and is used to map the hierarchy of computations to massively parallel computers with distributed memory system.


international conference on parallel processing | 1996

Estimating parallel execution time of loops with loop-carried dependences

Tsuneo Nakanishi; Kazuki Joe; Constantine D. Polychronopoulos; Keijiro Araki; Akira Fukuda

We propose a scheme to estimate exact minimum parallel execution time of the single loop with loop-carried dependences in medium and fine grain parallel execution. The minimum parallel execution time of a loop is given by the critical path length of the dependence graph which represents the code obtained from the fully unrolled loop. However, unrolling loops with a large number of iterations requires too much computation time and large storage space to be practical. The scheme proposed provides the minimum parallel execution time without unrolling the loop at all by reducing the problem into an integer linear programming problem and employing the simplex method and a branch-and-bound algorithm to solve it. We also show an experimental implementation of the proposed scheme with Livermore Benchmark Kernels to demonstrate that the computational complexity of our scheme is independent of the number of iterations of the given loop.


international conference on information networking | 2002

Evaluation of a Location Management System for Wireless Communicating Mobile Computers

Hideki Shimada; Shigeaki Tagashira; Tsuneo Nakanishi; Akira Fukuda

Mobile hosts can acquire location-dependent information at any place and be connected to a network from anywhere with wireless communication devices such as cellular phones, wireless LAN, etc. In such an environment we aim to construct a system software on which mobile hosts can share the location-dependent information with other hosts. It is, however, difficult for users who request location-dependent information to identify mobile hosts providing the information, since the system presents no mechanism to specify hosts by geographic location. In this paper we propose a location management system that manages locations of mobile hosts and enables users to specify location-dependent informations by their geographic locations. Since the location management system is employed for mobile computing, the system has the mechanism to reduce the overhead of location management on wireless communication. Moreover, we implement a part of this system and show that this system is suitable for mobile environment through the experiment.


languages and compilers for parallel computing | 1996

Estimating Minimum Execution Time of Perfect Loop Nests with Loop-Carried Dependences

Tsuneo Nakanishi; Kazuki Joe; Constantine D. Polychronopoulos; Keijiro Araki; Akira Fukuda

We propose a scheme to estimate exact minimum parallel execution time of perfect loop nests with loop-carried dependences at iteration and instruction-level parallelism. We formulate the problem of the estimation as an integer programming problem and solve it with a branch- and-bound scheme combined with the simplex method. Execution time obtained with the proposed scheme is useful to evaluate effects of applications of various optimization or parallelizing techniques for iteration or instruction-level parallel execution of loops.


languages and compilers for parallel computing | 1996

3D Visualization of Program Structure and Data Dependence for Parallelizing Compilers and Parallel Programming

Mariko Sasakura; Satoko Kiwada; Kazuki Joe; Tsuneo Nakanishi; Keijiro Araki

For effective use of parallel computers, a tool which assists users to know the way of parallelization is needed. Since we believe visualization is a useful tool for parallelization, we are developing a tool named NaraView for parallelizing Fortran programs. In this paper, we propose two visualization methods in NaraView, which are 3D visualization of program structure and data dependence.


한국멀티미디어학회지 | 2003

Design of WiPS : WLAN-Based Indoor Positioning System

Teruaki Kitasuka; Tsuneo Nakanishi; Akira Fukuda


Archive | 2005

Radio control chip set with positioning function, radio communication card with positioning function, radio terminal, and position measuring network system

Akira Fukuda; Teruaki Kitasuga; Kenji Kusumi; Tsuneo Nakanishi; 恒夫 中西; 憲嗣 久住; 輝明 北須賀; 晃 福田


Archive | 2002

Indoor Location Sensing Techinique using Wireless Network

Teruaki Kitasuka; Tsuneo Nakanishi; Akira Fukuda


情報処理学会研究報告システム評価(EVA) | 2002

Power Aware Dynamic Source Routing and Its Preliminary Evaluation

Taimei Ikeda; Teruaki Kitasuka; Tsuneo Nakanishi; Akira Fukuda

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Kazuki Joe

Nara Women's University

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Teruaki Kitasuka

Nara Institute of Science and Technology

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晃 福田

New York State Department of Environmental Conservation

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Constantine D. Polychronopoulos

University of Illinois at Urbana–Champaign

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