Tsunetoshi Arikado

First-principles studies of the intrinsic effect of nitrogen atoms on reduction in gate leakage current through Hf-based high-k dielectrics

The atomistic effects of N atoms on the leakage current through HfO2 high-k gate dielectrics have been studied from first-principles calculations within the framework of a generalized gradient approximation (GGA). It has been found that the intrinsic effects of N atoms drastically reduce the electron leakage current. N atoms couple favorably with oxygen vacancies (VO) in HfO2 and extract electrons from VO. As a result, VO energy levels are drastically elevated due to the charged-state change in VO from neutral (VO0) to positively charged (VO2+). Accordingly, N incorporation removes the electron leakage path mediated by VO related gap states.

Oxygen Vacancy Induced Substantial Threshold Voltage Shifts in the Hf-based High-K MISFET with p+poly-Si Gates -A Theoretical Approach

A theoretical investigation has been made of the origin of substantial threshold voltage (Vth) shifts observed in p+poly-Si gate Hf-based metal insulator semiconductor field effect transistors (MISFETs), by focusing on the effect of oxygen vacancy (VO) formation in HfO2. It has been found that VO formation and subsequent electron transfer across the interface definitely causes substantial Vth shifts, especially in p+poly-Si gate MISFETs. Moreover, the theory also systematically reproduces recent experimental reports that large flat band (Vfb) shifts are observed, even in intrinsic poly-Si gates, and that the Vfb shifts exhibit a high dependence on HfSiOx thickness.

Leakage Current Mechanism of Amorphous and Polycrystalline Ta[sub 2]O[sub 5] Films Grown by Chemical Vapor Deposition

The leakage current mechanism of the chemical vapor deposition Ta{sub 2}O{sub 5} film has been investigated. In the case of an as-deposited amorphous film, the presence of impurities such as carbon and hydrogen remaining in the film leads to the Poole-Frenkel type leakage current. The oxidation of these impurities results in a reduction in leakage current. O{sub 2} plasma is especially effective for oxidizing impurities, leading to a drastic reduction of the leakage current. However, O{sub 2} plasma cannot reduce the leakage current of the Ta{sub 2}O{sub 5} film crystallized at 700 C. This leakage current is not due to C and H, but rather to Si penetrated into the Ta{sub 2}O{sub 5} film from the underlying poly-Si electrode. Therefore, the amorphous Ta{sub 2}O{sub 5} film treated by O{sub 2} plasma is most suitable for use in stacked capacitors.

10-15 nm ultrashallow junction formation by flash-lamp annealing

Flash-lamp annealing (FLA) technology, a new method of activating implanted impurities, is proposed. FLA is able to reduce the time of the heating cycle to within the millisecond range. With this technology, an abrupt profile is realized, with a dopant concentration that can exceed the maximum carrier concentration obtained by conventional rapid thermal annealing (RTA) or furnace annealing. In contrast to a laser annealing method, FLA can activate dopants in an 8-inch-diameter substrate and, simultaneously, strictly control diffusion of dopants so as not to melt the substrate surface by radiation. FLA presents the possibility of fabricating sub-0.1-µm MOSFETs with good characteristics.

Improvement of threshold voltage deviation in damascene metal gate transistors

The metal gate work function deviation (crystal orientation deviation) was found to cause the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors. When the TiN work function (crystal orientation) is controlled by using the inorganic CVD technique, /spl Delta/V/sub th/ of the surface channel damascene metal gate (Al/TiN or W/TiN) transistors was drastically improved and found to be smaller than that for the conventional polysilicon gate transistors. The reason for the further reduction of the threshold voltage deviation (/spl Delta/V/sub th/) in the damascene metal gate transistors is considered to be that the thermal-damages and plasma-damages on gate and gate oxide are minimized in the damascene gate process. High performance sub-100 nm metal oxide semiconductor field effect transistors (MOSFETs) with work-function-controlled CVD-TiN metal-gate and Ta/sub 2/O/sub 5/ gate insulator are demonstrated in order to confirm the compatibility with high-k gate dielectrics and the technical advantages of the inorganic CVD-TiN.

Physical model of BTI, TDDB and SILC in HfO/sub 2/-based high-k gate dielectrics

The microscopic mechanism of the degradation occurring in HfO/sub 2/-based high-k/IL dual layer gate insulator has been investigated. The hole-injection-induced release of hydrogen from Si-H terminations causes IL-breakdown. This mechanism accelerates NBTI. Defects due to electron-trapped oxygen vacancies are the origin of trap-assisted tunneling, causing SILC in the electron current and PBTI.

Excimer-laser etching on silicon

Studies have been made of poly- and single Si etching induced by excimer-laser irradiation of the silicon surfaces in halogenated gases. Etching was investigated for different conduction types, impurity concentrations and crystallographic planes. Chlorine atoms accept electrons generated in photoexcited, undoped p-type Si, thus becoming negative ions which are pulled into the Si. However, the n+-type Si is etched spontaneously by Cl− as a result of the availability of conduction electrons. Fluorine atoms, with the highest electronegativity, take in electrons independent of whether the material is n- or p-type. And thus, the easy F− ion penetration into Si causes spontaneous etching in both types. New anisotropic etching for n+ poly-Si is investigated because of its importance to microfabrication technology. Methyl methacrylate (MMA) gas, which reacts with Cl atoms, produces a deposition film on the n+ poly-Si surface. The surface, from which the film is removed by KrF (5 eV) laser irradiation, is etched by Cl atoms, while the film remains on the side wall to protect undercutting. However, with the higher photon energy for the ArF (6.4 eV) laser, the Si-OH bonds are broken and electron traps are formed. These electrontrapping centers are easily annealed out in comparison to the plasma-induced centers. Pattern transfer etching for n+ poly-Si has been realized using reflective optics. The problems involved in obtaining finer resolution etching are discussed.

High performance damascene metal gate MOSFETs for 0.1 /spl mu/m regime

A novel transistor formation process (damascene gate process) was developed in order to apply metal gates and high dielectric constant gate insulators to MOSFET fabrication and minimize plasma damage to gate insulators. In this process, the gate insulators and gate electrodes are formed after ion implantation and high temperature annealing (/spl sim/1000/spl deg/C) for source/drain formation, and the gate electrodes are fabricated by chemical mechanical polishing (CMP) of gate materials deposited in grooves. Metal gates and high dielectric constant gate insulators are applicable to the MOSFET, since the processing temperature after gate formation can be reduced to as low as 450/spl deg/C. Furthermore, process-damages on gate insulators are minimized because there is no plasma damage caused by source/drain ion implantation and gate reactive ion etching (RIE). By using this process, fully planarized metal (W/TiN or Al/TiN) gate transistors with SiO/sub 2/ or Ta/sub 2/O/sub 5/ as gate insulators were uniformly fabricated on an 8-in wafer. Further, the damascene metal gate transistors exhibited low gate sheet resistivity, no gate depletion and drastic improvement in gate oxide integrity, resulting in high transistor performance.

Physics in Fermi level pinning at the polySi/Hf-based high-k oxide interface

We report that O vacancy (Vo) formation in ionic Hf-based dielectrics and subsequent electron transfer into poly Si gates across the interface, definitely cause substantial flat band (Vfb) shifts especially for p+ gate MISFETs. Our theory can systematically reproduce experiments related to Hf-based dielectrics, and gives a guiding principle towards gate/high-k oxide interface control.

Evaluation of transistor property variations within chips on 300-mm wafers using a new MOSFET array test structure

A new test structure has been designed to evaluate fluctuations of transistor properties, both within a chip and across a 300-mm wafer. The evaluation system was established with a conventional parametric tester and dc power supplies suitable for application on production lines. It was observed that threshold voltage (V/sub th/) variations increased with the reduction of the channel area. A difference was also observed in the standard deviation (/spl sigma//sub vt/) between NMOS and PMOS. From statistical evaluations, controlling CDs and improving rolloff characteristics were found to be important to reduce V/sub th/ variations.