Tsung-Hao Chen

Efficient large-scale power grid analysis based on preconditioned krylov-subspace iterative methods

In this paper, we propose preconditioned Krylov-subspace iterative methods to perform efficient DC and transient simulations for large-scale linear circuits with an emphasis on power delivery circuits. We also prove that a circuit with inductors can be simplified from MNA to NA format, and the matrix becomes an s.p.d matrix. This property makes it suitable for the conjugate gradient with incomplete Cholesky decomposition as the preconditioner, which is faster than other direct and iterative methods. Extensive experimental results on large-scale industrial power grid circuits show that our method is over 200 times faster for DC analysis and around 10 times faster for transient simulation compared to SPICE3. Furthermore, our algorithm reduces over 75% of memory usage than SPICE3 while the accuracy is not compromised.

Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing

Clock distribution is crucial for timing and design convergence in high-performance very large scale integration designs. Minimum-delay/power zero skew buffer insertion/sizing and wire-sizing problems have long been considered intractable. In this paper, we present ClockTune , a simultaneous buffer insertion/sizing and wire-sizing algorithm which guarantees zero skew and minimizes delay and power in polynomial time. Extensive experimental results show that our algorithm executes very efficiently. For example, ClockTune achieves 45/spl times/ delay improvement for buffering and sizing an industrial clock tree with 3101 sink nodes on a 1.2-GHz Pentium IV PC in 16 min, compared with the initial routing. Our algorithm can also be used to achieve useful clock skew to facilitate timing convergence and to incrementally adjust the clock tree for design convergence and explore delay-power tradeoffs during design cycles. ClockTune is available on the web (http://vlsi.ece.wisc.edu/Tools.htm).

INDUCTWISE: inductance-wise interconnect simulator and extractor

We develop a robust, efficient, and accurate tool, which integrates inductance extraction and simulation, called INDUCTWISE. This paper advances the state-of-the-art inductance extraction and simulation techniques and contains two major parts. In the first part, INDUCTWISE extractor, we discover the recently proposed inductance matrix sparsification algorithm, the K-method[1], albeit its great benefits of efficiency, has a major flaw on the stability. We provide both a counter example and a remedy for it. A window section algorithm is also presented to preserve the accuracy of the sparsification method. The second part, INDUCTWISE simulator, demonstrates great efficiency of integrating the nodal analysis formulation with the improved K-method. Experimental results show that INDUCTWISE has over 250x speedup compared to SPICE3. The proposed sparsification algorithm accelerates the simulator another 175x and speeds up the extractor 23.4x within 0.1% of error. INDUCTWISE can extract and simulate an 118K-conductor RKC circuit within 18 minutes. It has been well tested and released on the web for public usage. (http://vlsi.ece.wisc.edu/Inductwise.htm)

HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery

This paper proposes a general hierarchical analysis methodology, HiPRIME, to efficiently analyze RLKC power delivery systems. After partitioning the circuits into blocks, we develop and apply the IEKS (Improved Extended Krylov Subspace) method to build the multiport Norton equivalent circuits which transform all the internal sources to Norton current sources at ports. Since there are no active elements inside the Norton circuits, passive or realizable model order reduction techniques such as PRIMA can be applied. The significant speed improvement, 700 times faster than Spice with less than 0.2% error and 7 times faster than a state-of-the-art solver, InductWise, is observed. To further reduce the top-level hierarchy runtime, we develop a second-level model reduction algorithm and prove its passivity.

HiSIM: hierarchical interconnect-centric circuit simulator

To ensure the power and signal integrity of modern VLSI circuits, it is crucial to analyze huge amount of nonlinear devices together with enormous interconnect and even substrate parasitics to achieve the required accuracy. Neither traditional circuit simulation engines such as SPICE nor switch-level timing analysis algorithms are equipped to handle such a tremendous challenge in both efficiency and accuracy. We establish a solid framework that simultaneously takes advantage of a hierarchical nonlinear circuit simulation algorithm and an advanced large-scale linear circuit simulation method using a new predictor-corrector algorithm. Under solid convergence and stability guarantees, our simulator, HiSIM, a hierarchical interconnect-centric circuit simulator, is capable of handling the post-layout RLKC power and signal integrity analysis task efficiently and accurately. Experimental results demonstrate over 180X speed up over the conventional flat simulation method with SPICE-level accuracy.

SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation

The recent demand for system-on-chip RF mixed-signal designand aggressive supply-voltage reduction require chip-level accurateanalysis of both the substrate and power delivery systems.Together with the rising frequency, low-k dielectric, copper interconnects,and high conductivity substrate, the inductance effectsraised serious concern recently.However, the increasing designcomplexity creates tremendous challenges for chip-level power-deliverysubstrate co-analysis.In this paper, we propose a noveland efficient reluctance-based passive model order reduction techniqueto serve these tasks.Our work, SuPREME(Substrate andPower-delivery Reluctance-Enhanced Macromodel Evaluation) notonly greatly reduces the computational complexity of previousreluctance-based model order algorithms but is also capable ofhandling large number of noise sources efficiently.To facilitatethe analysis of inductive substrate return paths and evaluate thehigh-frequency substrate coupling effects, we derive a novel RLKCsubstrate model from Maxwells equations for the first time.Experimentalresults demonstrate the superior runtime and accuracyof SuPREME compared to the traditional MNA-based simulation.

PODEA: Power delivery efficient analysis with realizable model reduction

The huge number of independent sources of power delivery systems prevents the use of traditional model reduction algorithms due to the port domination nature. This paper presents an innovative RC model reduction method, PODEA, to analyze RC linear circuits with many dynamic independent sources. Based on the multi-port Norton theorem and model order reduction techniques, we develop and apply current source transformation algorithms to transform attached current sources from one node to neighboring nodes. Since there is no source attached, general RC reduction algorithms can be applied to eliminate the node. Experimental results demonstrate the efficiency and accuracy of the proposed PODEA algorithm. With linear running time, for an example with over 50,000 nodes, our reduction method only takes about 0.6 seconds while maintaining 1% error and 88% reduction ratio.

Frequency-dependent reluctance extraction

A new methodology is presented to captiire high frequency effects of interconnect, namely skin and proximity by using the reluctance (inverse inductance) method. As demonstrated in numerous publications that the reluctance method exhibits excellent locality and suitability of sparsification. The reluctance method results in great benefit in terms of efficiency of extraction and simulation. Mast of the previous studies described the reluctance extraction method without t,aking frequency dependent effects into consideration. In this paper, we first show the differences in frequency response between formula-based inductance extraction and frequency dependent inductance extraction to demonstrate the need to capture high frequency effect. Then a novel frequency dependent reluctance extraction method is proposed by using a robust windowing policy, which is able to handle irregular geometries in VLSI applications. Experimental results demonstrate the superior runtime and accuracy over traditional partial inductance extraction.