Peter Hazucha

Area-efficient linear regulator with ultra-fast load regulation

We demonstrate a fully integrated linear regulator for multisupply voltage microprocessors implemented in a 90 nm CMOS technology. Ultra-fast single-stage load regulation achieves a 0.54-ns response time at 94% current efficiency. For a 1.2-V input voltage and 0.9-V output voltage the regulator enables a 90 mV/sub P-P/ output droop for a 100-mA load step with only a small on-chip decoupling capacitor of 0.6 nF. By using a PMOS pull-up transistor in the output stage we achieved a small regulator area of 0.008 mm/sup 2/ and a minimum dropout voltage of 0.2 V for 100 mA of output current. The area for the 0.6-nF MOS capacitor is 0.090 mm/sup 2/.

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10/spl times/ better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits.

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled linearly with diode area. The measured SER per bit of SRAMs in 0.25 /spl mu/m, 0.18 /spl mu/m, 0.13 /spl mu/m, and 90 nm showed an increase of 8% per generation.

A 480-MHz, multi-phase interleaved buck DC-DC converter with hysteretic control

We propose an on-chip 1.8 V-to-0.9 V DC-DC converter aimed to reduce the input current and decoupling requirements of future microprocessors. By utilizing a 90-nm CMOS process, employing a four-phase hysteretic control, and operating at ultra-high frequency of 480-MHz, we achieved a 10% output droop with only 2.5 nF of on-chip decoupling, for 0.5 A of load current. No off-chip decoupling was connected to the output. At 480 MHz the measured efficiency was 72%. At 250 MHz, the efficiency improved to 76% at the cost of a 17% droop or larger decoupling of 11.5 nF. A converter with 100 A rating would require a capacitor of 0.5 /spl mu/F, which is comparable to the size of an on-chip capacitor of a typical microprocessor.

Integrated on-chip inductors using magnetic material (invited)

On-chip inductors with magnetic material are integrated into both advanced 130 and 90 nm complementary metal-oxide semiconductor processes. The inductors use aluminum or copper metallization and amorphous CoZrTa magnetic material. Increases in inductance of up to 28 times corresponding to inductance densities of up to 1.3 μ H / mm 2 were obtained, significantly greater than prior values for on-chip inductors. With such improvements, the effects of eddy currents, skin effect, and proximity effect become clearly visible at higher frequencies. The CoZrTa was chosen for its good combination of high permeability, good high-temperature stability ( > 250 ° C ) , high saturation magnetization, low magnetostriction, high resistivity, minimal hysteretic loss, and compatibility with silicon technology. The CoZrTa alloy can operate at frequencies up to 9.8 GHz , but trade-offs exist between frequency, inductance, and quality factor. The effects of increasing the magnetic thickness on the permeability spectra were measured and modeled. The inductors use magnetic vias and elongated structures to take advantage of the uniaxial magnetic anisotropy. Techniques are presented to extract a sheet inductance and examine the effects of magnetic vias on the inductors. The inductors with thick copper and thicker magnetic films have resistances as low as 0.04 Ω , and quality factors up to 8 at frequencies as low as 40 MHz.

Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation

Rapidly increasing input current of microprocessors resulted in rising cost and motherboard real estate occupied by decoupling capacitors and power routing. We show by analysis that an on-die switching DC-DC converter is feasible for future microprocessor power delivery. The DC-DC converter can be fabricated in an existing CMOS process (90nm-180nm) with a back-end thin-film inductor module. We show that 85% efficiency and 10% output voltage droop can be achieved for 4:1, 3:1, and 2:1 conversion ratios, area overhead of 5% and no additional on-die decoupling capacitance. A 4:1 conversion results in 3.4/spl times/ smaller input current and 6.8/spl times/ smaller external decoupling.

High-voltage power delivery through charge recycling

In this paper, we describe a technique for delivering power to a digital integrated circuit at high voltages, reducing current demands and easing requirements on power-ground network impedances. The design approach consists of stacking CMOS logic domains to operate from a voltage supply that is a multiple of the nominal supply voltage. DC-DC downconversion is performed using charge recycling without the need for explicit downconverters. Experimental results are presented for the prototype system in a 0.18-/spl mu/m CMOS technology operating at both 3.6 V and 5.4 V. Peak energy efficiencies as high as 93% are demonstrated at 3.6 V.

A Delay-Locked Loop Synchronization Scheme for High-Frequency Multiphase Hysteretic DC-DC Converters

This paper reports a delay locked loop (DLL) based hysteretic controller for high-frequency multiphase buck DC-DC converters. The DLL control loop employs the switching frequency from a hysteretic comparator to automatically synchronize the remaining phases. A dedicated duty cycle control loop is used to enable current sharing and ripple cancellation. We demonstrate a 25-70 MHz 4-phase converter with fast hysteretic control and output conversion range of 17%-80% while achieving a peak efficiency of 83% and peak-to-peak ripple within 10% in standard 0.6 mum 5 V CMOS process.

Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process. Accelerated measurements with a neutron beam at Los Alamos National Laboratory demonstrated 10/spl times/ better reliability of the SER-tolerant latch over the standard latch at no speed degradation. The worst case energy and area penalties were 39% and 44%, respectively. Both the energy and area penalties are negligible for standard-latch transistor sizes at least double the minimum width. We analyzed the effects of the recovery time, threshold voltage assignment, and leakage on the SER robustness. The proposed latch can improve reliability of critical sequential logic elements in microprocessors and other circuits.We measured neutron soft error rate (SER) of hardened and standard latches in a 90 nm dual-Vt CMOS process. The hardened latch demonstrated over 10/spl times/ lower SER at no speed degradation. Energy penalty can be minimal for standard-latch transistor sizes at least twice the minimum size. We analyzed the effects of recovery time and leakage on the SER robustness.