Tsung-Sum Lee

A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal

This paper describes the design strategy and implementation of a low-voltage pseudodifferential double-sampled timing-skew-insensitive sample-and-hold (S/H) circuit with low hold pedestal based on the Miller-effect scheme. The S/H circuit employs bootstrapped switches in order to facilitate low voltage operation. The design considerations for each building block are described in detail. The S/H circuit has been designed using a 0.35-/spl mu/m 2P4M CMOS technology and experimental results are presented. The 1.5-V S/H circuit operates up to a sampling frequency of 50 MHz with less than -54.6 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8 V/sub pp/. In these conditions, a differential hold pedestal of less than 0.8 mV, 1.6 ns acquisition time at 0.8-V step input, and 0.8 V/sub pp/ full-scale differential input range are achieved.

A low-voltage CMOS transconductor for VHF continuous-time filters

A new CMOS low-voltage transconductor suitable for VHF continuous-time filters is proposed. The output resistance of the transconductor is compensated and the resulting output resistance can be fine-tuned by means of a separate voltage. The transconductor has a large bandwidth due to excess phase compensation. The transconductance is tunable with the common-mode voltage. Further, it exhibit low distortion due to the used square-law linearization technique.

A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential double-sampled design relaxes the trade-off between sampling speed and the sampling precision. Simulation results are given to demonstrate the potential advantage of the new technique.

A fully differential low-voltage CMOS high-speed track-and-hold circuit

A new technique for realizing a fully differential low-voltage CMOS high-speed track-and-hold (T/H) circuit is presented. The design consideration of the building blocks is described in detailed. Simulation results are given to demonstrate the potential advantage of the new technique.

Two 1-V Fully Differential CMOS Switched-Capacitor Amplifiers

Two 1-V fully differential CMOS switched-capacitor amplifiers in a standard CMOS 0.35-μm technology are presented. The improved bootstrapped switches are used to allow rail-to-rail signal swing. The circuit design of the major building blocks is described. The performance of these two circuits is demonstrated by experimental results.

A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter

A 10-b 30-MS/s low power CMOS pipelined analog-to-digital converter (ADC) is described. A low-voltage technique is proposed for pipelined analog-to-digital converter that avoids the use of on-chip clock voltage doubler, multithreshold voltage process, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough and enhance the dynamic performance of the pipelined ADC. The cross-coupled configuration of multiplying digital-to-analog converter (MDAC) also provides an effective common-mode feedback to overcome the problem of common-mode accumulation. This design achieves DNL and INL of 0.38LSB and 0.46LSB respectively, while SNDR is 58.5dB and SFDR is 66.1dB at an input frequency of 12MHz. Operating at 30MS/S sampling rate under a single 1.5V power supply, the power consumption is 36.8mW in a 0.35 mum CMOS process. Simulations have been performed to demonstrate the feasibility of this new technique.

Design techniques for low-voltage fully differential CMOS switched-capacitor amplifiers

Two 1V fully differential CMOS switched-capacitor amplifiers in a standard CMOS 0.35mum technology are presented. The bootstrapped switches are used to allow rail-to-rail signal swing. The circuit design of major building blocks is described. The performance of these two circuits is demonstrated by simulation results

Design techniques for CMOS micropower low-voltage switched-capacitor delta-sigma modulator

The design of a micropower, low-voltage switched-capacitor delta-sigma modulator that consumes only 90 /spl mu/W at 1.5V supply is described. The modulator is designed employing bootstrapped switches in order to facilitate low voltage operation. Low power dissipation is obtained through the use of biasing some transistors in weak inversion. The delta-sigma modulator achieves an 88dB dynamic range and a peak signal to noise plus total harmonic distortion ratio of 67.1dB with a sampling rate of 1MHz and an oversampling ratio of 128.

A fully integrated MOSFET-C oscillator with precision amplitude control and self start-up

A novel MOSFET-C state variable oscillator is proposed. The circuit integrated in 0.8 /spl mu/m CMOS process provides precision control of both amplitude and frequency and is guaranteed to start oscillating. This readily integrable audio frequency, sinusoidal oscillator can achieve very low harmonic distortion. Experimental results are in accordance with the expected theoretical behavior.

A 0.6-V subthreshold-leakage supressed CMOS fully differential switched-capacitor amplifier

A 0.6-V subthreshold-leakage suppressed CMOS fully differential switched-capacitor amplifier using Analog T-switch scheme in a standard 0.18μm CMOS technology is presented. The circuit design of major building blocks is described. The performance of this circuit is demonstrated by experimental results. The experimental results confirm the capability of Analog T-switch scheme to fulfill circuit requirements.