Chi-Chang Lu

A 1.5-V 50-MHz pseudodifferential CMOS sample-and-hold circuit with low hold pedestal

This paper describes the design strategy and implementation of a low-voltage pseudodifferential double-sampled timing-skew-insensitive sample-and-hold (S/H) circuit with low hold pedestal based on the Miller-effect scheme. The S/H circuit employs bootstrapped switches in order to facilitate low voltage operation. The design considerations for each building block are described in detail. The S/H circuit has been designed using a 0.35-/spl mu/m 2P4M CMOS technology and experimental results are presented. The 1.5-V S/H circuit operates up to a sampling frequency of 50 MHz with less than -54.6 dB of total harmonic distortion for an input sinusoidal amplitude of 0.8 V/sub pp/. In these conditions, a differential hold pedestal of less than 0.8 mV, 1.6 ns acquisition time at 0.8-V step input, and 0.8 V/sub pp/ full-scale differential input range are achieved.

A 10-bit 60-MS/s Low-Power CMOS Pipelined Analog-to-Digital Converter

A 10-bit 60-MS/s low-power CMOS pipelined analog-to-digital converter (ADC) is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit is employed to enhance the dynamic performance of the pipelined ADC. Bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. Employing double sampling and bias current scaling techniques, very competitive power consumption can be achieved. The prototype chips have been fabricated and experimental results confirm the feasibility of this new technique.

A very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal

A new technique for realizing a very-high-speed low-power low-voltage fully differential CMOS sample-and-hold circuit with low hold pedestal is presented. The fully differential double-sampled design relaxes the trade-off between sampling speed and the sampling precision. Simulation results are given to demonstrate the potential advantage of the new technique.

A fully differential low-voltage CMOS high-speed track-and-hold circuit

A new technique for realizing a fully differential low-voltage CMOS high-speed track-and-hold (T/H) circuit is presented. The design consideration of the building blocks is described in detailed. Simulation results are given to demonstrate the potential advantage of the new technique.

Two 1-V Fully Differential CMOS Switched-Capacitor Amplifiers

Two 1-V fully differential CMOS switched-capacitor amplifiers in a standard CMOS 0.35-μm technology are presented. The improved bootstrapped switches are used to allow rail-to-rail signal swing. The circuit design of the major building blocks is described. The performance of these two circuits is demonstrated by experimental results.

A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital Converter

A 10-b 30-MS/s low power CMOS pipelined analog-to-digital converter (ADC) is described. A low-voltage technique is proposed for pipelined analog-to-digital converter that avoids the use of on-chip clock voltage doubler, multithreshold voltage process, bootstrapped switch, or switched-opamp technique. At the front-end, a low-voltage S/H circuit with cross-coupled input sampling switch is employed to eliminate the input signal feedthrough and enhance the dynamic performance of the pipelined ADC. The cross-coupled configuration of multiplying digital-to-analog converter (MDAC) also provides an effective common-mode feedback to overcome the problem of common-mode accumulation. This design achieves DNL and INL of 0.38LSB and 0.46LSB respectively, while SNDR is 58.5dB and SFDR is 66.1dB at an input frequency of 12MHz. Operating at 30MS/S sampling rate under a single 1.5V power supply, the power consumption is 36.8mW in a 0.35 mum CMOS process. Simulations have been performed to demonstrate the feasibility of this new technique.

A 1.2V 10-bit 5 MS/s CMOS cyclic ADC

A 1.2V 10-bit 5MS/s low power cyclic analog-to-digital converter (ADC) based on double-sampling technique is proposed. At the front-end, a timing-skew-insensitive double-sampled Miller-capacitance-based sample-and-hold circuit (S/H) is employed to enhance the dynamic performance of the cyclic ADC. Double sampling technique is also applied to multiplying digital-to-analog converter (MDAC). This scheme provides a better power efficiency for the proposed cyclic ADC. Furthermore, bootstrapped switch achieves rail-to-rail signal swing at low-voltage power supply. This ADC design achieves DNL and INL of 0.32LSB and 0.42LSB respectively, while SNDR is 56.7 dB and SFDR is 67.8 dB at an input frequency of 400 kHz. Operating at 5MS/s sampling rate under a single 1.2 V power supply, the power consumption is 3.6 mW in TSMC 0.18 m CMOS 1P6M process.

A 250MHz 11BIT 20mW low-hold-pedestal CMOS fully differential track-and-hold circuit

A new technique for realizing a very-high-speed low-power low-voltage CMOS fully differential track-and-hold circuit with low hold pedestal is presented. To achieve high sampling linearity the circuit utilizes improved bootstrapped input switch. The fully differential design relaxes the trade-off between sampling speed and the sampling precision. The circuit design of major building blocks is described in detailed. A prototype circuit in a 0.35-μ m CMOS process is integrated and experimental results are presented.

Two Fully Differential CMOS 1V Switched-Capacitor Amplifiers

Two fully differential CMOS 1V switched-capacitor amplifiers in a standard CMOS 0.35 mu m technology are presented. The improved bootstrapped switches are used to allow rail-to-rail signal swing. The circuit design of major building blocks is described. The performance of these two circuits is demonstrated by experimental results.

A 1.5V 12-b 40 MSamples/s CMOS pipelined ADC

A 12-b 40-MSamples/s low power CMOS pipelined analog-to-digital converter is described. A novel switched-capacitor multiply-by-two amplifier with an accurate gain of two is proposed for pipelined ADC. The proposed architecture requires only one opamp in four phases to generate two effective outputs. It significantly suppresses the gain error due to capacitor-mismatch and also provides a better power efficiency. This ADC design achieves DNL and INL of 0.38LSB and 0.48LSB respectively, while SNDR is 69.5dB and SFDR is 77.1dB at an input frequency of 10MHz. Operating at 40MS/s sampling rate under a single 1.5V power supply, the power consumption is 76.8mW in a 0.35jim CMOS process.