Tyler Kent

Atomic imaging of the irreversible sensing mechanism of NO2 adsorption on copper phthalocyanine.

Ambient NO2 adsorption onto copper(II) phthalocyanine (CuPc) monolayers is observed using ultrahigh vacuum (UHV) scanning tunneling microscopy (STM) to elucidate the molecular sensing mechanism in CuPc chemical vapor sensors. For low doses (1 ppm for 5 min) of NO2 at ambient temperatures, isolated chemisorption sites on the CuPc metal centers are observed in STM images. These chemisorbates almost completely desorb from the CuPc monolayer after annealing at 100 °C for 30 min. Conversely, for high NO2 doses (10 ppm for 5 min), the NO2 induces a fracture of the CuPc domains. This domain fracture can only be reversed by annealing above 150 °C, which is consistent with dissociative chemisorption into NO and atomic O accompanied by surface restructuring. This high stability implies that the domain fracture results from tightly bound adsorbates, such as atomic O. Existence of atomic O on or under the CuPc layer, which results in domain fracture, is revealed by XPS analysis and ozone-dosing experiments. The observed CuPc domain fracturing is consistent with a mechanism for the dosimetric sensing of NO2 and other reactive gases by CuPc organic thin film transistors (OTFTs).

Arsenic decapping and pre-atomic layer deposition trimethylaluminum passivation of Al2O3/InGaAs(100) interfaces

The interrelated effects of initial surface preparation and precursor predosing on defect passivation of atomic layer deposited (ALD) Al2O3/InGaAs(100) interfaces are investigated. Interface trap distributions are characterized by capacitance-voltage and conductance-voltage analysis of metal-oxide-semiconductor capacitors. Thermal desorption conditions for a protective As2 layer on the InGaAs surface and dosing conditions of trimethylaluminum prior to ALD-Al2O3 are varied to alter the interface trap densities. Experimental results are consistent with the predictions of ab initio electronic structure calculations showing that trimethylaluminum dosing of the As-rich In0.53Ga0.47As(100) surface suppresses interface traps by passivating As dangling bonds prior to the initiation of Al2O3 deposition.

InGaAs surface preparation for atomic layer deposition by hydrogen cleaning and improvement with high temperature anneal

Using in situ atomic scale imaging with scanning tunneling microscopy/spectroscopy, a combination of atomic hydrogen dosing, annealing, and trimethyl aluminum dosing is observed to produce an ordered unpinned passivation layer on an air exposed InGaAs(001)-(4 × 2) surface with only monatomic steps. This shows that conventional gate-last semiconductor processing can be employed to fabricate a variety of electronic devices, even on air exposed compound semiconductors.

Atomic imaging of atomic layer deposition oxide nucleation with trimethylaluminum on As-rich InGaAs(001) 2 × 4 vs Ga/In-rich InGaAs(001) 4 × 2

Formation of a contaminant free, flat, electrically passive interface to a gate oxide such as a-Al(2)O(3) is the critical step in fabricating III-V metal oxide semiconductor field effect transistors; while the bulk oxide is amorphous, the interface may need to be ordered to prevent electrical defect formation. A two temperature in situ cleaning process is shown to produce a clean, flat group III or group V rich InGaAs surface. The dependence of initial surface reconstruction and dosing temperature of the seeding of aluminum with trimethylaluminum dosing is observed to produce an ordered unpinned passivation layer on InGaAs(001)-(4 × 2) surface at sample temperatures below 190 °C. Conversely, the InGaAs(001)-(2 × 4) surface is shown to generate an unpinned passivation layer with a seeding temperature up to 280 °C. For both reconstructions, the chemical drive force is consistent with formation of As-Al-As bonds. The optimal seed layer protects the surface from background contamination.

Passivation of InGaAs(001)-(2 × 4) by Self-Limiting Chemical Vapor Deposition of a Silicon Hydride Control Layer.

A saturated Si-Hx seed layer for gate oxide or contact conductor ALD has been deposited via two separate self-limiting and saturating CVD processes on InGaAs(001)-(2 × 4) at substrate temperatures of 250 and 350 °C. For the first self-limiting process, a single silicon precursor, Si3H8, was dosed at a substrate temperature of 250 °C, and XPS results show the deposited silicon hydride layer saturated at about 4 monolayers of silicon coverage with hydrogen termination. STS results show the surface Fermi level remains unpinned following the deposition of the saturated silicon hydride layer, indicating the InGaAs surface dangling bonds are electrically passivated by Si-Hx. For the second self-limiting process, Si2Cl6 was dosed at a substrate temperature of 350 °C, and XPS results show the deposited silicon chloride layer saturated at about 2.5 monolayers of silicon coverage with chlorine termination. Atomic hydrogen produced by a thermal gas cracker was subsequently dosed at 350 °C to remove the Si-Cl termination by replacing with Si-H termination as confirmed by XPS, and STS results confirm the saturated Si-Hx bilayer leaves the InGaAs(001)-(2 × 4) surface Fermi level unpinned. Density function theory modeling of silicon hydride surface passivation shows an Si-Hx monolayer can remove all the dangling bonds and leave a charge balanced surface on InGaAs.

The influence of surface preparation on low temperature HfO2 ALD on InGaAs (001) and (110) surfaces

Current logic devices rely on 3D architectures, such as the tri-gate field effect transistor (finFET), which utilize the (001) and (110) crystal faces simultaneously thus requiring passivation methods for the (110) face in order to ensure a pristine 3D surface prior to further processing. Scanning tunneling microscopy (STM), x-ray photoelectron spectroscopy (XPS), and correlated electrical measurement on MOSCAPs were utilized to compare the effects of a previously developed in situ pre-atomic layer deposition (ALD) surface clean on the InGaAs (001) and (110) surfaces. Ex situ wet cleans are very effective on the (001) surface but not the (110) surface. Capacitance voltage indicated the (001) surface with no buffered oxide etch had a higher C(max) hypothesized to be a result of poor nucleation of HfO2 on the native oxide. An in situ pre-ALD surface clean employing both atomic H and trimethylaluminum (TMA) pre-pulsing, developed by Chobpattana et al. and Carter et al. for the (001) surface, was demonstrated to be effective on the (110) surface for producing low D(it) high C(ox) MOSCAPs. Including TMA in the pre-ALD surface clean resulted in reduction of the magnitude of the interface state capacitance. The XPS studies show the role of atomic H pre-pulsing is to remove both carbon and oxygen while STM shows the role of TMA pre-pulsing is to eliminate H induced etching. Devices fabricated at 120 °C and 300 °C were compared.

InGaAs (110) Surface Cleaning Using Atomic Hydrogen

A major obstacle facing III-V semiconductor based metal oxide semiconductor field effect transistors (MOSFETs) is the large density of trap states that exist at the semiconductor/oxide interface.[1] These trap states can pin the Fermi level preventing the MOSFET from acting as a switch in logic devices. Several sources of Fermi level pinning have been proposed including oxidation of the III-V substrate.[2, 3] In order to minimize the presence of III-V oxides it is crucial to employ either an ex-situ etch or to use an in-situ method such as atomic hydrogen cleaning.[4, 5] Although atomic H cleaning of III-V surfaces is well known, it has never been demonstrated on InGaAs (110) crystallographic faces. Furthermore, tri-gate field effect transistors (finFETs) have recently been employed in commercially available logic chips.[6] This unique device architecture allows for a reduction in short channel effects, minimization of the subthreshold swing, and a higher transconductance.[7] The InGaAs (110) surface would be the sidewalls of a vertically aligned (001) based finFETs.[8] Therefore, it is essential to find an in-situ method to efficiently remove any oxides or contamination from the (110) surfaces that is also compatible with the (001) surface. In this study, STM was employed to determine if atomic hydrogen can be used to remove the native oxide from air exposed InGaAs (110) samples. A post clean anneal was used to restore the surface to molecular beam epitaxy (MBE) levels of cleanliness.

Dual passivation of GaAs (110) surfaces using O2/H2O and trimethylaluminum

The nucleation and passivation of oxide deposition was studied on defect-free GaAs (110) surfaces to understand passivation of surfaces containing only III-V heterobonds. The passivation process on GaAs (110) was studied at the atomic level using scanning tunneling microscopy while the electronic structure was determined by scanning tunneling spectroscopy (STS). The bonding of the oxidant and reductant were modeled with density functional theory. To avoid Fermi level pinning during gate oxide atomic layer deposition, a dual passivation procedure was required using both a reductant, trimethylaluminum (TMA), and an oxidant, O2 or H2O. Dosing GaAs (110) with TMA resulted in the formation of an ordered complete monolayer of dimethylaluminum which passivates the group V dangling bonds but also forms metal-metal bonds with conduction band edge states. These edge states were suppressed by dosing the surface with oxidants O2 or H2O which selectively react with group III-aluminum bonds. The presence of an ordered Al monolayer with a high nucleation density was indirectly confirmed by XPS and STS.

Mechanism of dangling bond elimination on As-rich InGaAs surface

This work demonstrates with STM, STS, DFT, and device studies that TMA prepulsing on the As-rich InGaAs (2×4) surface reduces the trap state density by reducing As-As dimer bonds and As dangling bonds.

Low temperature thermal ALD of a SiNx interfacial diffusion barrier and interface passivation layer on SixGe1− x(001) and SixGe1− x(110)

Atomic layer deposition of a silicon rich SiNx layer on Si0.7Ge0.3(001), Si0.5Ge0.5(001), and Si0.5Ge0.5(110) surfaces has been achieved by sequential pulsing of Si2Cl6 and N2H4 precursors at a substrate temperature of 285 °C. XPS spectra show a higher binding energy shoulder peak on Si 2p indicative of SiOxNyClz bonding while Ge 2p and Ge 3d peaks show only a small amount of higher binding energy components consistent with only interfacial bonds, indicating the growth of SiOxNy on the SiGe surface with negligible subsurface reactions. Scanning tunneling spectroscopy measurements confirm that the SiNx interfacial layer forms an electrically passive surface on p-type Si0.70Ge0.30(001), Si0.50Ge0.50(110), and Si0.50Ge0.50(001) substrates as the surface Fermi level is unpinned and the electronic structure is free of states in the band gap. DFT calculations show that a Si rich a-SiO0.4N0,4 interlayer can produce lower interfacial defect density than stoichiometric a-SiO0.8N0.8, substoichiometric a-Si3N2, or stoichiometric a-Si3N4 interlayers by minimizing strain and bond breaking in the SiGe by the interlayer. Metal-oxide-semiconductor capacitors devices were fabricated on p-type Si0.7Ge0.3(001) and Si0.5Ge0.5(001) substrates with and without the insertion of an ALD SiOxNy interfacial layer, and the SiOxNy layer resulted in a decrease in interface state density near midgap with a comparable Cmax value.