Tz Cheng Chiu

Kirkendall void formation in eutectic SnPb solder joints on bare Cu and its effect on joint reliability

The electronic packaging industry has been using electroless Ni(P)∕immersion Au as bonding pads for solder joints. Because of the persistence of the black pad defect, which is due to cracks in the pad surface, the industry is looking for a replacement of the Ni(P) plating. Several Cu-based candidates have been suggested, but most of them will lead to the direct contact of solder with Cu in soldering. The fast reaction of solder with Cu, especially during solid state aging, may be a concern for the solder joint reliability if the package will be used in a high temperature environment and is highly stressed. In this work, the reaction of eutectic SnPb solder with electrodeposited laminate Cu is studied. Emphasis is given to the evolution of the microstructure in the interfacial region during solid state aging and its effect on solder joint reliability. A large number of Kirkendall voids were observed at the interface between Cu3Sn and Cu. The void formation resulted in weak bonding between solder and Cu and...

Effect of thermal aging on board level drop reliability for Pb-free BGA packages

The drive for Pb-free solders in the microelectronics industry presents several new reliability challenges. Examples include package compatibility with higher process temperatures, new solder compound failure mechanisms, and the selection of the proper Pb-free alloy to maximize product lifetime. In addition to the challenges posed by the Pb-free material conversion, the migration of market focus from desktop computing to portable applications is changing the critical system failure mode of interest from conventional temperature cycling (T/C) induced solder fatigue opens to drop impact induced solder joint fracture. In this paper a study was conducted to investigate the influence of intermetallic compound (IMC) growth on the solder joint reliability of Pb-free ball grid array (BGA) packages under drop loading conditions. Thermal aging at homologous temperatures between 0.76 and 0.91 with microstructural analysis was conducted to analyze the solid phase IMC growth at the solder to BGA pad interface. Component level,ball shear and pull tests were also conducted to investigate the aging effect on solder joint strength. A key finding from this work is that Kirkendall voids formed at the bulk solder to package bare Cu pad interface under relative low 100/spl deg/C aging. Void formation and coalesce is shown to be the dominant mechanism for solder joint strength and board level drop reliability degradation.

Constitutive Behavior of Sn3.8Ag0.7Cu and Sn1.0Ag0.5Cu Alloys at Creep and Low Strain Rate Regimes

Constitutive models for SnAgCu solder alloys are of great interest at the present. Commonly, constitutive models that have been successfully used in the past for Sn-Pb solders are used to describe the behavior of SnAgCu solder alloys. Two issues in the modeling of lead-free solders demand careful attention: 1) Lead-free solders show significantly different creep strain evolution with time, stress and temperature, and the assumption of evolution to steady state creep nearly instantaneously may not be valid in SnAgCu alloys and 2) Models derived from bulk sample test data may not be reliable when predicting deformation behavior at the solder interconnection level for lead-free solders due to the differences in the inherent microstructures at these different scales. In addition, the building of valid constitutive models from test data derived from tests on solder joints must de-convolute the effects of joint geometry and its influence on stress heterogeneity. Such issues have often received insufficient attention in prior constitutive modeling efforts. In this study all of the above issues are addressed in developing constitutive models of Sn3.8Ag0.7Cu and Sn1.0Ag0.5Cu solder alloys, which represent the extremes of Ag composition that have been mooted at the present time. The results of monotonic testing are reported for strain rates ranging from 4.02E-6 to 2.40E-3 s-1. The creep behavior at stress levels ranging from 7.8 to 52 MPa is also described. Both types of tests were performed at temperatures of 25degC, 75degC and 125degC. The popular Anand model and the classical time-hardening creep model are fit to the data, and the experimentally obtained model parameters are reported. The test data are compared against other reported data in the literature and conclusions are drawn on the plausible sources of error in the data reported in the prior literature.

Interface reliability assessments for copper/low-k products

Multiple new materials are being adopted by the semiconductor industry at a rapid rate for both semiconductor devices and packages. These advances are driving significant investigation into the impact of these materials on device and package reliability. Active investigation is focused on the impact of back-end-of-line (BEOL) processing on Cu/low-k reliability. This paper discusses Cu/low-k BEOL interfacial reliability issues and relates key items from the assembly process and packaging viewpoint that should be managed in order to prevent adverse assembly impact on BEOL interfacial reliability. Reliability failure mechanisms discussed include interface diffusion-controlled events such as the well-known example of Cu electromigration (EM), as well as stress-migration voiding. Interface defectivity impact on dielectric breakdown and leakage is discussed. Lastly, assessments of assembly impact on these Cu/low-k interfacial concerns are highlighted.

Warpage evolution of overmolded ball grid array package during post-mold curing thermal process

Abstract Two of the main driving forces for warpage deformation and residual stress in electronic packages are the thermal expansion mismatch between dissimilar package constituents and the crosslinking reaction of polymers during packaging thermal processes. For the purpose of quantitatively characterizing these two driving forces and assessing the process effect on warpage deformation, experimental and numerical analyses were applied to study the warpage evolution of overmolded ball grid array (BGA) package under post-mold curing (PMC) thermal histories. From in situ shadow Moire warpage analyses on bimaterial and package specimens, it was observed that, during the isothermal curing condition, a significant increase in specimen warpage occurred as a result of molding compound shrinkage. A numerical modeling procedure that incorporates the models for the thermochemical cure kinetics, the curing- and chemical aging-induced shrinkage strains, and the cure-dependent viscoelastic relaxation modulus for the molding compound was then applied to simulate and compare to the experimentally obtained warpage evolutions. It can be seen from the analysis results that the evolution of package warpage over multiple thermal histories can be superpositioned by the thermal expansion mismatch-driven warpage change during non-isothermal stages and the chemical shrinkage-induced warpage evolution during isothermal aging at temperatures above the material glass transition point.

Effects of Curing and Chemical Aging on Warpage—Characterization and Simulation

In this paper, the effect of the curing process on the warpage of an encapsulated electronic package is considered by using a coupled chemical-thermomechanical modeling methodology. A cure-dependent constitutive model that consists of a cure-kinetic model, a curing- and chemical-aging-induced shrinkage model, and a degree of cure-dependent viscoelastic relaxation model was developed and implemented in a numerical finite-element model for warpage simulation. Effects of polymerization conversion and chemical aging on the warpage evolution of a bimaterial dummy package after molding and during the postmold curing (PMC) process were investigated by using the proposed modeling methodology. Shadow Moiré warpage analyses were also performed to validate the numerical results. It was found from the warpage analyses that the chemical aging, while contributing little to the overall cross linking during the PMC, has a significant effect on the package warpage. The coupled chemical-thermomechanical model can be applied for performing numerical optimization for the packaging process and the assembly reliability.

Ball Grid Array Solder Joint Reliability Under System-Level Compressive Load

Heatsinks have been widely used in the electronics industry as a thermal solution for high-performance and highpower-density devices. The thermal efficiency of heatsink solutions may be improved by increasing the compressive load applied on the interface between the electronic package and heatsink. Typical approaches for heatsink retention, however, would also lead to high levels of compressive load on the package ball grid array (BGA) solder joints. In this paper, the effect of compressive load on SnPbAg solder joint reliability is investigated by using both experimental and numerical approaches. Accelerated system-level solder joint reliability tests under temperature cycling and isothermal aging conditions, with the presence of compressive loads, are first performed to identify and characterize the critical reliability failure mode. Creep constitutive behavior under compression is then characterized and implemented in numerical finite-element simulations for developing a phenomenological model of the BGA solder joint failure under compressive loading. A life prediction formula for SnPbAg solder joint subject to constant compressive load is also proposed.

Application of viscoelastic model for simulating process-induced warpage of ball grid array packages

Warpage evolution of an overmolded BGA package either under uniform temperature excursion or during post-mold curing process is analyzed by using finite element simulation with a cure-dependent viscoelastic model for the molding compound. Additional finite element analyses are performed to compare molding compound constitutive behavior (temperature-dependent elastic or viscoelastic) on the package warpage prediction. Through shadow Moiré experimental validation, it is observed that the prediction with viscoelastic constitutive model agrees well to the measured values; while the elastic model overestimates package warpage.

Interconnect reliability modeling for lead-free fan-out chip scale package

The fan-out-type chip scale package (fan-out CSP) is an embedded chip packaging technology that eliminates the need for wirebonds and flip-chip bumps. In this study, the board-level reliability of fan-out CSP is studied by using three-dimensional finite element analysis. A design of simulations study is applied to investigate the influences of package geometry on the board-level interconnect reliability of fan-out CSP. Results of the analysis indicate that better board-level reliability for the fan-out CSP can be achieved by using a thicker die with thinner molding compound. In addition, the response surface model obtained from the design of simulations study can be served as the basis for further fan-out CSP design optimization.

On the Homogenization of Multilayered Interconnect for Interfacial Fracture Analysis

The interface crack problem for Cu/low-k interconnect is considered using global-and-local finite element analysis. In the global analysis the thin film interconnect is represented by a homogenized layer with equivalent material properties. Local model around the interface crack tip is analyzed with displacement boundary condition extracted from the global modeling result to determine the fracture mechanics parameters. It is shown that, for the global-and-local modeling approach, interconnect homogenization using representative volume element (RVE) approach provides accurate prediction on the fracture mechanics parameters for an interface crack under either thermal or mechanical loads, while significant error occurs when the interconnect, even though having thickness less than 1/100 of the whole component thickness, is neglected in the global analysis. The problem of an interface crack between low-k dielectric and etch-stop thin film in a flip-chip package under thermal excursion is also investigated as an application example of the global-and-local modeling approach.