Tzvetan S. Metodi

A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation

Recent experimental advances have demonstrated technologies capable of supporting scalable quantum computation. A critical next step is how to put those technologies together into a scalable, fault-tolerant system that is also feasible. We propose a quantum logic array (QLA) microarchitecture that forms the foundation of such a system. The QLA focuses on the communication resources necessary to efficiently support fault-tolerant computations. We leverage the extensive groundwork in quantum error correction theory and provide analysis that shows that our system is both asymptotically and empirically fault tolerant. Specifically, we use the QLA to implement a hierarchical, array-based design and a logarithmic expense quantum-teleportation communication protocol. Our goal is to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution that plague current proposals for large-scale quantum computing. Our work complements recent work by Balenseifer et al. (2005), which studies the software tool chain necessary to simplify development of quantum applications; here we focus on modeling a full-scale optimized microarchitecture for scalable computing.

A pageable, defect-tolerant nanoscale memory system

As we scale down to the nanoscale regime, manufacturing defects will increase significantly. With expected bit error rates as high as 2-10 %, the reliability of a contiguous 4 K-byte memory page falls off to zero. We propose a powerful combination of static and dynamic techniques to tackle this problem. Using a combination of defect mapping, error correction, and sparing, we can achieve approximately 46.5%, 26.1% and 13.2% storage efficiency in contiguous 4 K-byte pages, given bit error rates of 2%, 5% and 10%, respectively. This result allows us to use standard virtual memory to map a contiguous virtual address space onto a nanoscale memory system with some bad physical pages, giving us a more usable system than previous approaches.

Combining static and dynamic defect-tolerance techniques for nanoscale memory systems

Nanoscale technology promises dramatically increased device density, but also decreased reliability. With bit error rates projected to be as high as 10%, designing a usable nanoscale memory system poses a significant challenge. In particular, we need to bootstrap a sea of unreliable bits into contiguous address ranges which are preferably as large as 4K-byte virtual memory pages. We accomplish this bootstrapping through a combination of dynamic error correction codes within 32-bit blocks and a static defect map which tracks usability of these blocks. The key insight is that statically-determined defect locations can be much more powerful than dynamically correcting for unknown locations, but that defect maps are only practical at a coarse granularity. Using a combination of BCH error correction codes and a Bloom-Filter-based defect map, we achieve a memory efficiency of 60% and 13% for 4K-byte pages at 1% and 10% bit-error rates, respectively.

High-level interconnect model for the quantum logic array architecture

We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportation-based logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution over large distances. The QLAs logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048-bit number using Shors quantum factoring algorithm. Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.

Quantum Computing for Computer Architects, Second Edition

Quantum computers can (in theory) solve certain problems far faster than a classical computer running any known classical algorithm. While existing technologies for building quantum computers are in their infancy, it is not too early to consider their scalability and reliability in the context of the design of large-scale quantum computers. To architect such systems, one must understand what it takes to design and model a balanced, fault-tolerant quantum computer architecture. The goal of this lecture is to provide architectural abstractions for the design of a quantum computer and to explore the systems-level challenges in achieving scalable, fault-tolerant quantum computation. In this lecture, we provide an engineering-oriented introduction to quantum computation with an overview of the theory behind key quantum algorithms. Next, we look at architectural case studies based upon experimental data and future projections for quantum computation implemented using trapped ions. While we focus here on architectures targeted for realization using trapped ions, the techniques for quantum computer architecture design, quantum fault-tolerance, and compilation described in this lecture are applicable to many other physical technologies that may be viable candidates for building a large-scale quantum computing system. We also discuss general issues involved with programming a quantum computer as well as a discussion of work on quantum architectures based on quantum teleportation. Finally, we consider some of the open issues remaining in the design of quantum computers. Table of Contents: Introduction / Basic Elements for Quantum Computation / Key Quantum Algorithms / Building Reliable and Scalable Quantum Architectures / Simulation of Quantum Computation / Architectural Elements / Case Study: The Quantum Logic Array Architecture / Programming the Quantum Architecture / Using the QLA for Quantum Simulation: The Transverse Ising Model / Teleportation-Based Quantum Architectures / Concluding Remarks

Scheduling physical operations in a quantum information processor

Irrespective of the underlying technology used to implement a large-scale quantum architecture system, one of the central challenges of accurately modeling the architecture is the ability to map and schedule a quantum application onto a physical grid while taking into account the cost of communication, the classical resources, and the maximum exploitable parallelism. In this paper we introduce and evaluate a physical operations scheduler for arbitrary quantum circuits. Our scheduler accepts a description of a circuit together with a description of a specific physical layout and outputs a sequence of operations that expose the required communication and available parallelism in the circuit. The output of the scheduler is a quantum assembly language file that can directly be simulated on a set of available tools.

A realizable distributed ion-trap quantum computer

Recent advances in trapped ion technology have rapidly accelerated efforts to construct a near-term, scalable quantum computer. Micro-machined electrodes in silicon are expected to trap hundreds of ions, each representing quantum bits, on a single chip. We find, however, that scalable systems must be composed of multiple chips and we explore inter-chip communication technologies. Specifically, we explore the parallelization of modular exponentiation, the substantially dominant portion of Shors algorithm, on multi-chip ion-trap systems with photon-mediated communication between chips. Shors algorithm, which factors the product of two primes in polynomial time on quantum computers, has strong implications for public-key cryptography and has been the driving application behind much of the research in quantum computing. Parallelization of the algorithm is necessary to obtain tractable execution times on large problems. Our results indicate that a 1024-bit RSA key can be factored in 13 days given 4300 (each of area 10 by 10 centimeters) ion-trap chips in a multi-chip system.

Design-space exploration of fault-tolerant building blocks for large-scale quantum computing

In this paper, we present a design methodology for quantifying the role each building component of a logical fault-tolerant building block for quantum computers plays in the performance of the logical block. A logical building block is the set of operations necessary to execute a fault-tolerant circuit structure in quantum programs, such as the network of operations implementing a logical quantum bit. By analyzing the interaction between the algorithmic structure of a building block and the number of lower-level elements where faults are likely to occur, we can quantify the sensitivity of logical building blocks to two things: (1) to changes in the failure rates of the lower level elements comprising a proposed microarchitecture model, which are defined as logic gates, memory mechanisms, and data communication mechanisms; and (2) to transformation of the program structure for each building block through compilation techniques. We further show how this information can be used to develop optimized building blocks by inserting the gathered design constraints in our compilation mechanisms.

Investigation of the classically controlled ion-motion interface in a multiplexed ion-trap quantum computer

We design and implement a SIMD scheduler that returns the distribution of quantum operations when taking into account communication and layout constraints. We define the ion-motion path interface for trapped ion quantum computing architectures and analyze the design constraints involved in assembling the control circuitry necessary to implement this interface. Finally, we describe an Instruction Set Architecture (ISA) that we can use to optimize and provide a library of fault-tolerant building blocks for scalable quantum computation.