Darshan D. Thaker

A Quantum Logic Array Microarchitecture: Scalable Quantum Data Movement and Computation

Recent experimental advances have demonstrated technologies capable of supporting scalable quantum computation. A critical next step is how to put those technologies together into a scalable, fault-tolerant system that is also feasible. We propose a quantum logic array (QLA) microarchitecture that forms the foundation of such a system. The QLA focuses on the communication resources necessary to efficiently support fault-tolerant computations. We leverage the extensive groundwork in quantum error correction theory and provide analysis that shows that our system is both asymptotically and empirically fault tolerant. Specifically, we use the QLA to implement a hierarchical, array-based design and a logarithmic expense quantum-teleportation communication protocol. Our goal is to overcome the primary scalability challenges of reliability, communication, and quantum resource distribution that plague current proposals for large-scale quantum computing. Our work complements recent work by Balenseifer et al. (2005), which studies the software tool chain necessary to simplify development of quantum applications; here we focus on modeling a full-scale optimized microarchitecture for scalable computing.

Efficient fault tolerance in multi-media applications through selective instruction replication

As voltages decrease, soft errors are expected to become an increasing problem in maintaining program correctness. Unfortunately, previous mechanisms to improve processor reliability protect all processor instructions equally, causing such approaches to suffer from significant performance degradation and/or substantial hardware overhead. However, recent research has shown that in multimedia applications such as photography, video, and audio, not all instructions are created equal: many operations prove to be far more tolerant to faults than others [1]. This observation can be leveraged to limit the cost of reliable computing by protecting only those instructions that are critical to correct execution. We propose a mechanism to protect against soft errors through selective instruction replication. We begin with a dynamic instruction replication framework that replicates every instruction and checks them upon commit, rolling back for any inconsistent results. Instead of replicating the entire program, instructions that the compiler identifies as tolerant to error would remain unprotected. While full replication requires 40% to 100% overhead, our mechanism requires only 30% to 75% overhead, reducing the overhead by 15-33% with minimal hardware overhead. We suffer only 0.5 - 1% fidelity degradation with this approach.

Recursive TMR: scaling fault tolerance in the nanoscale era

As process technologies decrease in feature size, designers face new reliability challenges. Feature sizes of less than 0.25 /spl mu/m increase the risk of noise-related faults that result from electrical disturbances in the logic values held in circuits and on wires. Such transient faults can cause single-bit upsets, which in turn can introduce a logical fault in the circuit. In this article, we classify the sources of noise that can be scalably corrected (where using RTMR is beneficial as device size scales) with recursive triple modular redundancy (RTMR) and those that cannot. In particular, we have found that single-event upsets caused by energetic particles can be effectively compensated with RTMR. Flicker noise in devices, however, is not competitively correctable. In other words, noise models show that an RTMR circuit composed of small, less reliable devices does not always compete in speed and area with an equivalent circuit composed of large more reliable devices. In light of this finding, we discuss microarchitectural design options for mixing large and small devices to trade off reliability, speed, and area.

High-level interconnect model for the quantum logic array architecture

We summarize the main characteristics of the quantum logic array (QLA) architecture with a careful look at the key issues not described in the original conference publications: primarily, the teleportation-based logical interconnect. The design goal of the the quantum logic array architecture is to illustrate a model for a large-scale quantum architecture that solves the primary challenges of system-level reliability and data distribution over large distances. The QLAs logical interconnect design, which employs the quantum repeater protocol, is in principle capable of supporting the communication requirements for applications as large as the factoring of a 2048-bit number using Shors quantum factoring algorithm. Our physical-level assumptions and architectural component validations are based on the trapped ion technology for implementing quantum computing.

Scheduling physical operations in a quantum information processor

Irrespective of the underlying technology used to implement a large-scale quantum architecture system, one of the central challenges of accurately modeling the architecture is the ability to map and schedule a quantum application onto a physical grid while taking into account the cost of communication, the classical resources, and the maximum exploitable parallelism. In this paper we introduce and evaluate a physical operations scheduler for arbitrary quantum circuits. Our scheduler accepts a description of a circuit together with a description of a specific physical layout and outputs a sequence of operations that expose the required communication and available parallelism in the circuit. The output of the scheduler is a quantum assembly language file that can directly be simulated on a set of available tools.

Circuit interfaces and optimization for resistive nanosensors

Carbon nanotube and semiconductor nanowires could potentially usher in a new era in chemical detection for environmental, biomedical, and security applications by providing highly sensitive detection at very low cost. For wireless sensor networks and implantable biomedical sensing devices, system power consumption is a critical factor in determining volume, operating lifetime, and circuit performance. We describe several key circuit challenges related to interfacing variable resistance nanosensors to digital integrated circuits through analog-to-digital data conversion. These challenges include drift in nanosensor baseline resistance due to fabrication variances and incomplete chemical desorption, various sensor and circuit noise sources, and integrated sensor and circuit area and power tradeoffs. We describe and evaluate the potential of several circuit techniques to address these issues, including self-test, self-calibration, and noise cancellation. Simulations indicate that +/- 40% variations in fabricated baseline resistance can be reduced to +/- 2% with a 25% increase in sensing area using a configurable sensor design. Based on these results, we explore potential A/D converter architectures for their use as low power nanosensor interfaces. Finally, we discuss resolution limits to miniaturization of nanosensor interface circuits.

A realizable distributed ion-trap quantum computer

Recent advances in trapped ion technology have rapidly accelerated efforts to construct a near-term, scalable quantum computer. Micro-machined electrodes in silicon are expected to trap hundreds of ions, each representing quantum bits, on a single chip. We find, however, that scalable systems must be composed of multiple chips and we explore inter-chip communication technologies. Specifically, we explore the parallelization of modular exponentiation, the substantially dominant portion of Shors algorithm, on multi-chip ion-trap systems with photon-mediated communication between chips. Shors algorithm, which factors the product of two primes in polynomial time on quantum computers, has strong implications for public-key cryptography and has been the driving application behind much of the research in quantum computing. Parallelization of the algorithm is necessary to obtain tractable execution times on large problems. Our results indicate that a 1024-bit RSA key can be factored in 13 days given 4300 (each of area 10 by 10 centimeters) ion-trap chips in a multi-chip system.

Simulation tools to study a distributed shared memory for clusters of symmetric multiprocessors

Distributed shared memory (DSM) systems have become popular as a means of utilizing clusters of computers for solving large applications. We have developed a high-performance DSM, Strings. In addition, to improve the performance of our DSM, a memory hierarchy simulator has been developed that allows us to compare various techniques very quickly and with much less effort. This paper describes our simulator, DSMSim. We show that the simulators performance closely matches the real system and demonstrate potential performance gains of up to 60% after adding optimization features to the simulator. The simulator also accepts the same code as the software distributed shared memory.

Experiments with Parallelizing Tribology Simulations

Different parallelization methods vary in their system requirements, programming styles, efficiency of exploring parallelism, and the application characteristics they can handle. For different situations, they can exhibit totally different performance gains. This paper compares OpenMP, MPI, and Strings for parallelizing a complicated tribology problem. The problem size and computing infrastructure is changed to assess the impact of this on various parallelization methods. All of them exhibit good performance improvements and it exhibits the necessity and importance of applying parallelization in this field.

Experiments with parallelizing a tribology application

Different parallelization methods vary in their system requirements, programming styles, efficiency of exploring parallelism, and the application characteristics they can handle. Different applications can exhibit totally different performance gains depending on the parallelization method used. The paper compares OpenMP, MPI, and Strings (a distributed shared memory) for parallelizing a complicated tribology problem. The problem size and computing infrastructure are changed and their impacts on the parallelization methods are studied. All of the methods studied exhibit good performance improvements. The paper exhibits the benefits that are the result of applying parallelization techniques to applications in this field.