Ullrich R. Pfeiffer

A 0.65 THz Focal-Plane Array in a Quarter-Micron CMOS Process Technology

A focal-plane array (FPA) for room-temperature detection of 0.65-THz radiation has been fully integrated in a low-cost 0.25 mum CMOS process technology. The circuit architecture is based on the principle of distributed resistive self-mixing and facilitates broadband direct detection well beyond the cutoff frequency of the technology. The 3 timesZ 5 pixel array consists of differential on-chip patch antennas, NMOS direct detectors, and integrated 43-dB voltage amplifiers. At 0.65 THz the FPA achieves a responsivity (Rv) of 80 kV/W and a noise equivalent power (NEP) of 300 pW/ radic{Hz}. Active multi-pixel imaging of postal envelopes demonstrates the FPAs potential for future cost-effective terahertz imaging solutions.

Rational design of high-responsivity detectors of terahertz radiation based on distributed self-mixing in silicon field-effect transistors

In search of novel detectors of electromagnetic radiation at terahertz frequencies, field-effect transistors (FETs) have recently gained much attention. The current literature studies them with respect to the excitation of plasma waves in the two-dimensional channel. Circuit aspects have been taken into account only to a limited degree. In this paper, we focus on embedding silicon FETs in a proper circuitry to optimize their responsivity to terahertz radiation. This includes impedance-matched antenna coupling and amplification of the rectified signal. Special attention is given to the investigation of high-frequency short-circuiting of the gate and drain contacts by a capacitive shunt, a common approach of high-frequency electronics to induce resistive mixing in transistors. We theoretically study the effect of shunting in the framework of the Dyakonov–Shur plasma-wave theory, with the following key results. In the quasistatic limit, the capacitive shunt induces the longitudinal high-frequency field neede...

A 1 k-Pixel Video Camera for 0.7–1.1 Terahertz Imaging Applications in 65-nm CMOS

A 1 k-pixel camera chip for active terahertz video recording at room-temperature has been fully integrated in a 65-nm CMOS bulk process technology. The 32 × 32 pixel array consists of 1024 differential on-chip ring antennas coupled to NMOS direct detectors operated well-beyond their cutoff frequency based on the principle of distributed resistive self-mixing. It includes row and column select and integrate-and-dump circuitry capable of capturing terahertz videos up to 500 fps. The camera chip has been packaged together with a 41.7-dBi silicon lens (measured at 856 GHz) in a 5 × 5 × 3 cm3 camera module. It is designed for continuous-wave illumination (no lock-in technique required). In this video-mode the camera operates up to 500 fps. At 856 GHz it achieves a responsivity Rv of about 115 kV/W (incl. a 5-dB VGA gain) and a total noise equivalent power (NEPtotal) of about 12 nW integrated over its 500-kHz video bandwidth. At a 5-kHz chopping frequency (non-video mode) a single pixel can provide a maximum responsivity Rv of 140 kV/W (incl. a 5-dB VGA gain) and a minimum noise equivalent power ( NEP) of 100 pW/√Hz at 856 GHz. The wide-band antenna and pixel design achieves a 3-dB bandwidth of at least 790-960 GHz.

Active 220- and 325-GHz Frequency Multiplier Chains in an SiGe HBT Technology

A 325-GHz ×18 frequency multiplier chain implemented in a fτ/fmax = 250 GHz/380 GHz evaluation SiGe heterojunction bipolar transistor technology is presented. The chain achieves a peak output power of -3 dBm and consists of a balanced doubler driven by two cascaded tripler stages. It operates from 317 to 328 GHz with a 0-dBm 18-GHz input signal and a 1.5-W power consumption. Additionally, 220- and 325-GHz doubler breakout circuits with integrated driver amplifiers are presented. The doublers reach an output power of -1 dBm at 220 GHz and -3 dBm at 325 GHz with a power dissipation of 630 and 420 mW, respectively.

Subharmonic 220- and 320-GHz SiGe HBT Receiver Front-Ends

Monolithically integrated 220- and 320-GHz receiver front-ends manufactured in an engineering version of anfT/fmax=280/435-GHz SiGe technology are presented. Subharmonic mixing is provided by a Gilbert cell with stacked switching quads fed by quadrature 110/160-GHz local oscillator (LO) signals. The 220-GHz version of the front-end is equipped with an integrated LNA with a measured 15-dB gain and 28-GHz bandwidth. This front-end yields a conversion gain of 16 dB, an 18-dB single-sideband (SSB) noise figure (NF), and a 30-GHz bandwidth when pumped with a 0-dBm 110-GHz LO signal. The 320-GHz version of the front-end omits the low-noise amplifier and features an integrated × 9 LO multiplier chain to facilitate operation and characterization. A conversion gain of -14 dB and a 36-dB SSB NF is obtained over the 313-to-328-GHz frequency range. The presented circuits demonstrate that a fully integrated receiver front-end can be implemented up to submillimeter-wave frequencies in an SiGe HBT technology.

Terahertz heterodyne detection with silicon field-effect transistors

We report on the detection of electromagnetic radiation at 0.65 THz by silicon field-effect transistors operated in heterodyne mode. Aiming at terahertz imaging with numerous pixels in a focal-plane array, we explore the improvement of the dynamic range achieved over power detection when the local-oscillator (LO) power is distributed quasioptically onto all detectors. These consist of resonantly antenna-coupled complementary metal-oxide-semiconductor transistors with a gate length of 0.25 μm, and each has an integrated voltage amplifier. With a LO power of 2 μW per detector, the noise-equivalent power amounts to 8 fW/Hz, leading to an estimated improvement of the dynamic range by 29 dB.

A 288-GHz Lens-Integrated Balanced Triple-Push Source in a 65-nm CMOS Technology

A 288-GHz lens-integrated high-power source implemented in a 65-nm CMOS technology is presented. The source consists of two free-running triple-push ring oscillators locked out-of phase by magnetic coupling. The oscillators drive a differential on-chip ring antenna, which illuminates a hyper-hemispherical silicon lens through the backside of the die. An on-wafer breakout of the oscillators core achieves a peak output power of -1.5 dBm with a 275-mW DC power consumption. The radiated power of the packaged source is -4.1 dBm, which is the highest reported radiated power of a single CMOS source beyond 200 GHz. The source die including the antenna occupies only 500 x 570 μ m2.

A 1kpixel CMOS camera chip for 25fps real-time terahertz imaging applications

Future imaging applications in the submillimeter-Wave range (300GHz to 3THz) require RF systems that can achieve high sensitivity and portability at low power consumption levels. In particular, CMOS process technologies are attractive due to their low price tag for industrial, surveillance, scientific, and medical applications. Recently, CMOS-based detectors have shown good sensitivity up to 1THz with NEPs on the order of 66pW/√(Hz) at 1THz [1]. However, CMOS terahertz imagers developed thus far have only operated single detectors based on lock-in measurement techniques to acquire raster-scanned images with frame rates on the order of minutes [2]. To address these impediments, we present a low-power 1kpixel terahertz camera chip fully compliant with an industrial 65nm ft/fmax=160GHz/200GHz CMOS process technology. The active-pixel circuit topology is designed to accommodate the optics for wide bandwidth (0.6 to 1THz) in stand-off detection with a 40dBi Si-lens. It includes row/col select and integrate-and-dump circuitry capable of capturing terahertz images with video frame rates up to 25fps at a power consumption of 2.5μW/pixel.

Terahertz imaging with Si MOSFET focal-plane arrays

We report on imaging at terahertz frequencies using a 3x5 Si MOSFET focal-plane array (FPA) processed by a 0.25-μm CMOS technology. Each pixel of the FPA consists of a 645-GHz patch antenna coupled to a FET detector and a 43-dB voltage amplifier with a 1.6-MHz bandwidth. We achieve a typical single-pixel responsivity of 80 kV/W and a noise-equivalent power (NEP) of 300 pW/√Hz at 30-kHz. The performance data of these all-CMOS devices pave the way for the realization of broad-band THz detectors and FPAs for video-rate active imaging on the basis of established low-cost and integration-friendly CMOS technology.

A Fully Integrated 240-GHz Direct-Conversion Quadrature Transmitter and Receiver Chipset in SiGe Technology

This paper presents a fully integrated direct-conversion quadrature transmitter and receiver chipset at 240 GHz. It is implemented in a 0.13-μm SiGe bipolar-CMOS technology. A wideband frequency multiplier (×16) based local-oscillator (LO) signal source and a wideband on-chip antenna designed to be used with an external replaceable silicon lens makes this chipset suited for applications requiring fixed and tunable LO. The chipset is packaged in a low-cost FR4 printed circuit board resulting in a complete solution with compact form-factor. At 236 GHz, the effective-isotropic-radiated-power is 21.86 dBm and the minimum single-sideband noise figure is 15 dB. The usable RF bandwidth for this chipset is 65 GHz and the 6-dB bandwidth is 17 GHz. At the system level, we demonstrate a high data-rate communication system where an external modem is operated in its two IF-bandwidth modes (250 MHz and 1 GHz). For the quadrature phase-shift keying modulation scheme, the measured data rate is 2.73 Gb/s (modem 1-GHz IF) with bit-error rate of 10-9 for a 15-cm link. The estimated data rate over the 17-GHz RF bandwidth is, hence, 23.025 Gb/s. Also, higher order modulation schemes like 16 quadrature amplitude modulation (QAM) with a data rate of 0.677 Gb/s and 64-QAM with a data rate of 1.0154 Gb/s (modem 250-MHz IF) is demonstrated. A second application demonstrator is presented where the wide tunable RF bandwidth of the chipset is used for material characterization. It is used to characterize an FR4 material (DE104) over the 215-260-GHz range.