Janusz Grzyb

Electrical characterization of textile transmission lines

In this paper, electrical characterization and modeling of conductive textiles are presented. A dedicated measurement setup has been developed to allow reliable connection of the textile samples with the equipment cables. Geometrical fabric structures and fabrication tolerances as well as high frequency properties up to 6 GHz for four types of textiles have been determined. Transmission lines with controlled characteristic impedance have been realized enabling the characterization of typical line attenuation factors. This work shows that textile transmission lines can be used for frequencies up to 1.2 GHz and 120 MHz with the maximal lengths of 10 and 100 cm, respectively.

An investigation of the material and process parameters for thin-film MCM-D and MCM-L technologies up to 100GHz

extraction and separation of dielectric material parameters and metalization-related process properties up to mm-wave frequencies based on the measurements of general microstrip lines set of different line cross-sections and lengths. The the microstrip line cross-sections and dielectric materials used withm the frame of the EU project LIPS aimed at the development of the low-cost packaging technologies at mmwave frequencies. The technology set covers BCB thin-film MCM-D and thin laminate MCM-L technologies. The procedure allows the separation of complex permittivity of dielectric materials and metalization process related parameters withnut an exact modelling of these latter ones, which is very complicated, especially for composite metal build-up. Not only standard single layer substrate microstrip confgurations can be analyzed but also more realistic in interconnect teclmology composite dielectric substrates and substrates with passivation layer configuration. In the first step of the procedure the complex propagation constants and complex characteristic impedances are extracted based on the probetip measurements of the microstrip lmes with two different lenghts. In the second step these parameters are converted into the C, G, L, R equivalent elements of the corresponding distributed circuit model for quasi-TEM lines. These are related to the dielectric material and metalizationrelated process parameters by the use of a set of non-linear closed-form equations. The latter ones are solved by the use 3. The 10w-frequencY caused of Newton method. Hundreds of full-wave simulations have been done to choose, test and modify the closed-form equations as they impose a limit on the maximal achievable accuracy of the extraction procedure. This limit defined by a general rms accuracy of the extracted dielectric constants has been calculated using a data set from above mentioned fullwave simulations and is below 0.7% for the technology set and microstrip dimensions used withm the project. Any measurements and process errors and tolerances are excluded because they are technology dependent.

MM-wave microstrip patch and slot antennas on low cost large area panel MCM-D substrates-a feasibility and performance study

This paper analyzes the performance and feasibility of microstrip patch and slot antennas on low-cost thin film MCM-D in the MM-wave frequency range. The critical parameters of millimeter design such as losses, bandwidth, and radiation pattern are discussed based on EM modeling and design examples of microstrip patch and compact rectangular slot loop antennas in the frequency range of 40-85 GHz. Simple technology modifications are pointed out to overcome the basic limitations of the patch antennas on thin films such as low efficiency and low bandwidth. To perform this feasibility study, a finite element method (FEM) is used as a simulation tool and HP8510XF vector network analyzer (VNA) as measurement equipment.

MCM-D technology for realisation of low cost system-on-package concept at 60-80 GHz

Proposes a global solution for the low-cost integration of a whole 60-80 GHz system including antenna arrays in MCM-L/D technology. The performance and feasibility of integrated slot and patch antennas for high directivity demanding applications is demonstrated, pointing at the microstrip patch array as a simpler solution. Both microstrip and CPW approach for the realisation of transmission media and distributed passives have also been analysed. The high performance of this solution has been demonstrated based on some examples such as: Wilkinson divider, branch-line coupler, a rat-race and a 4th order band-pass filter. Both microstrip and CPW resistors have been evaluated and parasitic effect compensating techniques have been proposed. The performance of via-based loads in microstrip configuration differs slightly from their via-less CPW counterparts. The ultimate MCM-D/L mixed solution with the appropriate BCB and laminate thicknesses has been proposed, which allows integration of high-performance interconnections, distributed passives; and flat high-efficiency patch antenna arrays.

MM-wave integrated antennas on low cost MCM-D substrates

This paper discusses the EM modelling and practical design of millimeter wave microstrip patch elements in the frequency range of 80 GHz on low cost MCM-D substrates. The critical parameters of millimeter-wave design such as losses, bandwidth and the influence of process tolerances on antenna performance are discussed.

Characteristic Impedance Deembeding of Printed Lines with the Probe-Tips Calibrations

The procedures allowing determination of the microstrip and CPW lines characteristic impedance are presented. The procedures are based on the measurement technique of two on-wafer line standards as presented by Carchon et al (1). An initial off-wafer LRM or TRL calibration is assumed. The formulation of the whole extraction problem in terms of the ABCD chain matrix allows us to omit the influence of a difference between complex characteristic impedances of both lines on the S-matrix asymmetry of the feeding transition. On the contrary, the AD-BC=1 condition of its chain matrix is not influenced by this effect. The next novelty lies in the modelling of the CPW-microstrip transition by a symmetric model. This allows to extract the characteristic impedance without using of any fixed transition model and takes automatically into consideration a distributed nature of the transition. The next feature is that a specific treatment of the measured standards enables to extract an equivalent position of the probe-tips along the line. In case of MCM-D different microstrip feed topologies have been analysed and the best possible one has been found.

Experimental analysis of design options for spiral inductors integrated on low cost MCM-D substrates

This paper presents the results of investigations on integrated inductors for a new low cost MCM-D substrate technology. The results are focused on the analysis of design options and design parameter for planar spiral inductors. Measurements on test structures were used to quantify process tolerances and inductor performance and to set up accurate models for EM-simulations. Simulation results of many different inductor configurations and layouts were compared in terms of inductance L, quality factor Q and area A. The goal was to give a better understanding of inductor behavior to geometry changes and to offer inductor design guidelines for RF system designers. Special attention was given to inductor cost, driven by area consumption.

Finite-width CBCPW characteristic impedance de-embedding with probe-tips

A characteristic impedance de-embedding technique of conductor-backed CPW (CBCPW) lines with probe-tip measurements and with automatic detection of the equivalent reference plane position is presented. The measurements up to 100 GHz, supported by full-wave finite element method (FEM) simulations, indicate some deviations in the extracted values as a result of the conversion to the waveguide modes.

Low-latency optoelectronic processor-memory interconnection demonstrator

A principal performance limitation of current computers is memory access latency. The random access time of DRAM can be as low as 20 ns but the overhead imposed by communication latency can increase the retrieval time to 150 ns in single processor systems or 1 ms in large multiprocessor systems. Optically interconnected VLSI offers the possibility of reductions in the communication component of memory latency of an order of magnitude. The improvement arises from the potential of direct high bandwidth low-latency links between any one chip and each one of a set of others. This potential principally arises from the ease of an optical implementation of fan-out and fan-in operations, together with the intrinsically high bandwidth of optical links. We have designed a scaleable system of processor-memory interconnections to explore this technology. Optical fan-out and fan-in modules will link a single processor to a bank of memory chips. The approach allows for multiple processors to be connected to multiple memory banks in an analogous fashion. The demonstrator will use 1-D VCSEL and photodiode arrays to provide optical i/o for the CPU and memory chips. The optical fan-out, fan-in and image relay can be implemented using an integrated planar optical system.

RF characterization of low cost MCM-D substrates, manufactured on large area panels

This article presents the RF characterization results of a large-area MCM-D technology developed within the EU LAP project. Microstrip lines were simulated, designed, and manufactured in several material combinations. Measurements up to 120 GHz showed good coincidence between simulation and reality. Future work is dedicated to filters and antennas in the 77 GHz range.