Ulrich Kleine

An automated design tool for analog layouts

In this paper, a layout synthesis tool for the design of analog integrated circuits (ICs) is presented. This tool offers great flexibility that allows analog circuit designers to bring their special design knowledge and experiences into the synthesis process to create high-quality analog circuit layouts. Different from conventional layout systems that are limited to the optimization of single devices, our layout generation tool attempts to optimize more complex modules. This tool includes a complete tool suite that covers the following three major analog physical designs stages. 1) Module Generation: designers can develop and maintain their own technology- and application-independent module generators for subcircuits using an in-house developed description language. 2) Placement: a two-stage placement technique, tailored for the analog placement design, is proposed. In particular, this placement algorithm features a novel genetic placement stage followed by a fast simulated reannealing scheme. 3) Routing: the minimum-Steiner-tree-based global routing is developed, and it is actually integrated into the placement procedure to improve reliability and routability of the placement solutions. Following the global routing, a compaction-based constructive detailed routing finally completes the interconnection of the entire layout. Several testing circuits have been applied to demonstrate the design efficiency and the effectiveness of this tool. Experimental results show that this new layout tool is capable of producing high quality layouts comparable to those manually done by layout experts but with much less design time

Symbolic pole/zero calculation using SANTAFE

The aim of symbolic analysis is to gain insight into circuit behavior. Therefore, in general, the location of the poles and zeros has to be known, which cannot be calculated symbolically for polynomials with degree greater than four. The CAD tool SANTAFE (Symbolic Analysis of Transfer Functions) applies the signal-flow graph method which tries to keep the result in a factorized form. The graphic view provided by a signal-flow graph is more visual and, as will be demonstrated, enables the user to perform circuit knowledge based approximations. A novel procedure based on symbolic Newton iteration accurately calculates high order transfer functions in the desired pole/zero form. In this way an Op-Amp was realized in a 1 ¿m 4 GHz BiCMOS process.

Design of nonlinear analog switched-capacitor circuits using building blocks

This paper describes an approach to the design of nonlinear analog switched-capacitor (SC) circuits using building blocks. First, we derive a number of nonlinear SC circuits, such as comparators, Schmitttriggers, waveform generators, etc., using stray-insensitive integrators and amplifiers. Then, as an example, an interpolative A/D converter and an FSK modulator design will be discussed and their integration in silicon-gate CMOS technology will be presented. Finally, a design example of an FSK demodulator with an SC phase-locked loop will be demonstrated.

Design of Bireciprocal Wave Digital Filters for High Sampling Rate Applications

Abst rac t : In this paper, the realization of bireciprocal wave digital filters (WDFs) in a dedicated bit-parallel architecture will be described. These filters are especially attractive for high sampling rate applications. The required hardware for a realization in dedicated hardware is reduced to less than half while the circuits can operate about twice as fast compared to other WDFs. A suitable WDF structure has been selected which contains a minimum number of operations to be carried out consecutively in the directed loops. To increase the operating rate of the filters the carry-save approach is chosen. It will be shown ho w stability of the filters is ensured in such a redundant number system and how overflow can be handled. An example of a WDF adaptor in carry-save technique will be given.

A novel analog module generator environment

This paper describes a novel analog module generator environment for the automatic layout development of analog circuits. The C++ tool features a novel procedural layout description language that drastically eases the creation of analog modules. Due to the object oriented programming the designer can specify the modules in a hierarchical way using elementary geometrical primitives and conditional statements. The primitive objects are placed relatively and are abutted with the help of a special compactor. An optimization routine with backtracking capability facilitates the creation of high quality analog layouts. A layout example of a broad-band BiCMOS amplifier demonstrates the usability of the tool.

Placement Algorithm in Analog-Layout Designs

Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this problem by using the optimization flow of a genetic algorithm (GA) enhanced by simulated annealing (SA). The bit-matrix representation is employed to improve the search efficiency. In particular, to reduce the solution space without degrading search opportunities, the technique of cell slide is deployed to transform an absolute placement to a relative placement. Following this cell-slide process, it is proved that, for an initial placement, there always exists a solution that can guarantee no occurrence of overlaps among cells and meet any applicable symmetry constraints pertaining to analog layouts. For the optimization of the algorithm parameters, the fractional factorial experiment using an orthogonal array has been conducted, and the exact parameter values are determined using a meta-GA approach. The experimental results show that, compared with the SA approach, the proposed algorithm consumes less computation time while generating higher quality layouts, comparable to expert manual placements

A novel class of complementary folded-cascode opamps for low voltage

Three novel complementary folded-cascode operational amplifiers (opamps) with high gain, large bandwidth, and rail-to-rail input range for low-voltage operation will be presented. These opamps feature high bandwidth due to minimum internal nodes. The output swing is increased by properly adjusting the output cascode transistor gate voltages close to the power supply voltages. The opamps have been fabricated with a standard 0.8-/spl mu/m CMOS technology. Measurements show the amplification is between 60.1 and 72.4 dB, and the unity gain bandwidth is 14 MHz for a 5-pF load, 2.5-V power supply, and 150-/spl mu/A bias current.

Real-time programmable low power SC bandpass filter

A real-time programmable switched-capacitor (SC) 2nd order bandpass filter is presented. It is based on voltage inverter switch (VIS) principle using inverse recharging devices. These devices are realized with dynamic amplifiers in order to achieve low power dissipation. The filter contains only grounded or virtually grounded network capacitances and therefore it is insensitive to the parasitics between the bottom plates of the implemented MOS capacitors and the substrate. It offers digital programming capability (two Q-factors and three center frequencies) and low power dissipation (185 μW at sampling frequency 8 kHz and power supply voltage 10 V). The filter has been integrated in standard CMOS metal-gate technology.

Wave digital filters using carry-save arithmetic

A carry-save approach for the implementation of high-speed bit-parallel recursive digital filters is presented. Special mapping rules for translating a carry-propagate arithmetic into a carry-save arithmetic are described and finite wordlength effects, especially carry-save saturation characteristics and the truncation behavior, are considered to ensure the stability of the filters. The proposed carry-save arithmetics ensure the full pseudopassivity and the forced response stability of the circuits. The carry-save technique is illustrated with an example of a third-order lattice wave digital filter.<<ETX>>

Switched-capacitor FSK modulator and demodulator in CMOS technology

Switched-capacitor FSK modulator and demodulator have been designed and fabricated in silicon-gate CMOS technology. The modulator is based on a programmable SC harmonic oscillator, while the demodulator features an SC phase-locked loop.