Usha Mehta

Survey of Test Data Compression Technique Emphasizing Code Based Schemes

As a result of the emergence of new fabrication technologies and design complexities, standard stuck-at scan tests are no longer sufficient. The number of tests and corresponding data volume increase with each new fabrication process technology. The demand goes to well beyond 100X tester cycle reduction considering new fault models. The test data compression has been an emerging need of VLSI field and the hot topic of research for last decade. Still there is a great need and scope for further reduction in test data volume. This reduction must be lossless for input side test data. This paper summarizes the different methods based on coding theory applied for lossless compression of the input side test data. It covers starting with simple code based methods to combine/hybrid methods. The basic goal here is to prepare survey on current methodologies applied for test data compression and prepare a platform for further development in this avenue.

Modified Selective Huffman Coding for Optimization of Test Data Compression, Test Application Time and Area Overhead

A compression-decompression scheme, Modified Selective Huffman (MS-Huffman) scheme based on Huffman code is proposed in this paper. This scheme aims at optimization of the parameters that influence the test cost reduction: the compression ratio, on-chip decoder area overhead and overall test application time. Theoretically, it is proved that the proposed scheme gives the better test data compression compared to very recently proposed encoding schemes for any test set. It is clearly demonstrated with a large number of experimental results that the proposed scheme improves the test data compression, reduces overall test application time and on-chip area overhead compared to other Huffman code based schemes.

Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead

The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In this paper, the five different approaches for don’t care bit filling based on nature of runs are proposed. These methods are used here to predict the maximum compression based on entropy relevant to different run length based data compression code. These methods are also analyzed for test power and area overhead corresponding to run length based codes. The results are shown with various ISCAS circuits.

Frequency Dependant Bit Appending: An Enhancement to Statistical Codes for Test Data Compression

Test data compression is a basic necessity for todays test methodology with reference to test cost and test time. This paper presents a compression/decompression scheme based on Frequency Dependant Bit Appending of test vector used with statistical codes. In the proposed scheme, the emphasis is not only on data compression but it aims the data compression with a smaller amount of silicon area overhead for on chip decoder. We have observed that when the number of bits per test vector is prime number or multiplication of prime number (particularly multiplied by 2 or 3), statistical codes gives a large area overhead. The proposed scheme of Frequency Dependant Bit Appending (FDBA) shows that in such cases, if we append few bits at the end of test vector before compression, it improves % compression with very less area overhead. With ISCAS benchmark circuits, it has been shown that when the proposed scheme is applied with statistical coding method, it not only improves % compression, but the area overhead is reduced a lot compared to the base statistical method.

Suitability of various low-power testing techniques for IP core-based SoC: a survey

Test power is the major issue for current generation VLSI testing. It has become the biggest concern for todays SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.

Development of Radiation Hardened by Design(RHBD) primitive gates using 0.18μm CMOS technology

Radiation Hardened By Design (RHBD) combinational circuits/primitive gates using 0.18um CMOS Technology is developed for Space application with help of Cogenda TCAD software suite. The proposed combinational cells are investigated for radiation simulation using three dimensional (3D) device structure. Single Event Transient (SET) caused by proton, α particle and heavy ions like C, Ar and Kr is observed on developed Cells and SET pulse width is measured on primitive gates. The proposed C element based radiation hardened Inverter is simulated using α, Ar and proton energetic particle. Proposed NOR and NAND gates are simulated under the radiation of proton, α and Kr and Single Event Transient Pulse Width is measured.

Defect characterization and testing of QCA devices and circuits: A survey

QCA (Quantum-dot Cellular Automata) is the promising future nanotechnology for computing. In QCA, the cells must be aligned properly at nano scales for proper functioning. Defects may occur in synthesis and deposition phase. So the defect analyses and testing cannot be ignored. This paper presents a survey on QCA basics, defect characterization and various testing aspects of QCA.

Fault analysis of QCA combinational circuit at layout & logic level

QCA (Quantum-dot Cellular Automata) is the most capable future nanotechnology for computing. Defects are most likely to occur in QCA devices due to the nanoscale Faults caused by these defects must be analyzed. This paper implement the QCA combinational circuit, half adder for which fault analysis is carried out. This paper presents the fault analysis of QCA combinational circuit, half adder at layout level using QCADesigner tool and at logic level using Hardware description Language for QCA (HDLQ).

Improvement in error resilience for compressed VLSI test data using Hamming code based technique

In the current scenario of IP core based SoC, to reduce the test time and test cost, the test data is preprocessed and compressed heavily. This compressed test data are transferred from Automatic Test Equipment (ATE) to chip under test through a serial communication link and will be decompressed on-chip before applying to actual DUT. If there is a problem with this link, there may be a flip in bit of test data. Compared to uncompressed test data, if there is a bit flip in the compressed data, the codeword may change and hence the decompressed data will have a large number of bit deviation. This deviation in bits can severely degrade the test quality and overall fault coverage which may affect yield. The error resilience is the capability of the test data to resist against such bit flips. Here in this paper, the earlier methods of error resilience is compared and a Hamming code based error resilience technique is proposed to improve the error resilience capacity of compressed test data. This method is applied on Huffman code based compressed test data of widely used ISCAS benchmark circuits. The fault coverage measurement results show the effectiveness of the proposed method. The basic goal here is to survey the effect of bit flips on fault coverage and prepare a platform for further development in this avenue.

Development of Controllability Observability Aided Combinational ATPG with Fault Reduction

With the increase improvement in VLSI design and progressive complication of circuits, an efficient technique for test pattern generation is necessary with the intension of reducing number of faults and with use of testability measures. Using the fault equivalence method, the number of faults are reduced. The line justification and error propagation is used to find the test vectors for reduced fault set with the aid of controllability and observability. The programs are developed for fault equivalence method, controllability observability and finally for automatic test pattern generation using object oriented language C++. ISCAS 85 C17 circuit is used for analysis purpose. Standard ISCAS (International Symposium on Circuits And Systems) netlist format is used. The stuck at fault model is considered. The complete ATPG based on controllability and observability for reduced fault set is discussed in this paper.