N. M. Devashrayee

Hamming Distance Based Reordering and Columnwise Bit Stuffing with Difference Vector: A Better Scheme for Test Data Compression with Run Length Based Codes

Because of increased design complexity and advanced fabrication technologies, the number of tests and corresponding data volume increases rapidly. As the large size of test data volume is becoming one of the major problems in testing System-on-a-Chip (SoC), several compression coding schemes have been proposed in past. Run Length Coding is one of the most familiar coding methodologies for compression. In this paper, we present a new scheme named Hamming Distance Based Reordering and Column wise Bit Stuffing with Difference Vector (HDR-CBS-DV), which can be used with any run length based code technique for better compression ratio. Four techniques have been applied in this scheme: Selection of first vector, Hamming Distance Based Reordering, Columnwise Bit Stuffing and Difference Vector. Instead of directly applying any known run length code like Golomb, Frequency Directed Run Length (FDR), Extended FDR (EFDR), Modified FDR (MDFR) or Shifted Alternate FDR (SAFDR) to given test set, if we apply the proposed scheme to test set prior to applying the run length base code, the compression obtained is improved drastically. The experimental results on ISCAS89 Benchmark circuits shows that the test data compression ratio improves significantly for each case. It is also noteworthy that in most of the case, this scheme does not involve any extra silicon area over-head compared to the base code with which it used. For few cases, it requires an extra XOR gate and feedback path only. The proposed scheme can be easily integrated into the existing industrial flow.

Diffusivity of Al in Ti and the effect of Si doping for very large scale integrated circuit interconnect metallization

Interaction between Ti/Al and Ti/AlSi layered structures is studied by the resistivity measurements. The change in the resistivity of the structure is correlated to the rate of formation of an intermetallic transition metal compound due to interaction between Al and Ti. It is found that the presence of Si inhibits the interaction. As the reaction rate of the intermetallic compound formation is reduced the activation energy increases. The diffusion coefficient of Al in Ti reduces to a value 6.6×10−17 from 6×10−14 cm2/s and the amount of Ti consumed is reduced by about two orders of magnitude at 450 °C for Ti/AlSi. The results are discussed and implications for multilevel metallization are pointed out.

Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead

The data compression of any partially specified test data depends upon how the unspecified bits are filled with 1s and 0s. In this paper, the five different approaches for don’t care bit filling based on nature of runs are proposed. These methods are used here to predict the maximum compression based on entropy relevant to different run length based data compression code. These methods are also analyzed for test power and area overhead corresponding to run length based codes. The results are shown with various ISCAS circuits.

Frequency Dependant Bit Appending: An Enhancement to Statistical Codes for Test Data Compression

Test data compression is a basic necessity for todays test methodology with reference to test cost and test time. This paper presents a compression/decompression scheme based on Frequency Dependant Bit Appending of test vector used with statistical codes. In the proposed scheme, the emphasis is not only on data compression but it aims the data compression with a smaller amount of silicon area overhead for on chip decoder. We have observed that when the number of bits per test vector is prime number or multiplication of prime number (particularly multiplied by 2 or 3), statistical codes gives a large area overhead. The proposed scheme of Frequency Dependant Bit Appending (FDBA) shows that in such cases, if we append few bits at the end of test vector before compression, it improves % compression with very less area overhead. With ISCAS benchmark circuits, it has been shown that when the proposed scheme is applied with statistical coding method, it not only improves % compression, but the area overhead is reduced a lot compared to the base statistical method.

Low Voltage, Low Power Folding Amplifier for Folding & Interpolating ADC

The folding and interpolating ADC has speed advantage similar to flash ADC with reduced complexity. The folding amplifier can be used to produce more than one zero-crossing point to reduce required number of comparators. This paper presents simple low voltage, low power folding amplifier with folding factor=4 for folding and interpolating ADC. The design is implemented using 0.13um technology at 1.5V supply voltage. The simulation results are compared with voltage mode (conventional differential pair based) folding amplifier and current steering folding amplifier. In order to achieve low power, glitches are reduced. The simulation result indicates that the proposed folding amplifier work faster compared to other two designs.

On the fabrication of thin film MICs from substrate cleaning to pattern delineation

Abstract The processing technology for fabricating thin film MICs is discussed. All the process steps starting from the ceramic substrate cleaning, the substrate metallization with NiCr-Cu-Au sputtered layers, photolithography and the chemical etching are described. The practical problems, important precautions and the optimized processing parameters for the development of reproducible MICs is presented.

Suitability of various low-power testing techniques for IP core-based SoC: a survey

Test power is the major issue for current generation VLSI testing. It has become the biggest concern for todays SoC. While reducing the design efforts, the modular design approach in SoC (i.e., use of IP cores in SoC) has further exaggerated the test power issue. It is not easy to select an effective low-power testing strategy from a large pool of diverse available techniques. To find the proper solutions for test power reduction strategy for IP core-based SoC, in this paper, starting from the terminology and models for power consumption during test, the state of the art in low-power testing is presented. The paper contains the detailed survey on various power reduction techniques proposed for all aspects of testing like external testing, Built-In Self-Test techniques, and the advances in DFT techniques emphasizing low power. Further, all the available low-power testing techniques are strongly analyzed for their suitability to IP core-based SoC.

Low Power Folding and Interpolating ADC Using 0.18 mu-m Technology

Folding and interpolating A/D converters have been shown to be an effective means of digitization of high bandwidth signals at intermediate resolution. The paper focuses on design of low power 5-bit folding & interpolating ADC. The folding amplifier can be used to produce more than one zero-crossing point to reduce required number of comparators. The converter is designed using novel low voltage, low power folding amplifier with folding factor=4. The folding amplifier is used in the design of coarse and fine converter both. To reduce the power consumption, encoder based on XOR-OR logic is used. The design is implemented using 0.18mm technology at 1.7V supply voltage.

Development and performance characterization of the lightly doped drain MOS transistor

Abstract The lightly doped drain transistor is an important technology to reduce hot electron degradation in near and sub-micron devices. The developmental work for establishing an LDD technology is reported. The salient features of this work are: fabrication of a 1-μm gate length LDD MOS transistor, establishment of a new C-V technique for identification of LDD structure and characterization of hot electron generation and degradation. The results are compared for a normal transistor and an LDD transistor with difference schedules. It is shown that the degradation is reduced for a critical range of n− concentration and is a complex function of many process parameters.

Design and analysis of low-power high-speed shared charge reset technique based dynamic latch comparator

Circuit intricacy, high-speed, low-power, small area requirement, and high resolution are crucial factors for high-speed and low-power applications like analog-to-digital converters (ADCs). The delay analysis of classical dynamic latch comparators is presented to add more insight of their design parameters, which effects the performance parameter. In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and requires smaller die area. The proposed comparator benefits from a new shared charge logic based reset technique to achieve high-speed with low-power consumption. It is shown by simulation and analysis that the delay time is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 90nm CMOS technology. The results show that, for the proposed comparator, the delay is 51.7 ps and consumes only 33.62 W power, at 1V supply voltage and 1GHz clock frequency. In addition, the proposed dynamic latch comparator has a layout size of 7.2m8.1m.