Uwe Scheuermann

Reliability challenges of automotive power electronics.

Abstract A high reliability of power electronic modules is an essential requirement for hybrid traction applications. This includes a high capability to withstand the stress of repeated active and passive thermal cycles in order to meet the lifetime requirements. Active power cycling requirements are not especially severe for hybrid traction applications compared to many industrial applications. The lifetime for passive thermal cycles by a change of ambient conditions in contrast is defined by the materials and the architecture of a power module. The classical module design with Cu base plates is limited in lifetime particularly with respect to passive temperature cycles due to CTE mismatch. The advanced pressure contact design eliminates the base plate together with the base plate solder and the terminal solder interconnections and thus enhances the thermal cycling capability. As a synergy effect, this design establishes a very balanced static and transient current distribution for paralleled chips. Finally, the last remaining solder interface – the chip solder layer – can be replaced by an Ag diffusion sinter technology. The presented cycling test results will confirm, that the first 100% solder-free module shows an improved performance in passive and active cycling tests.

Power cycling results for different control strategies

Power cycling is an important method to characterize the lifetime of power semiconductor modules. Application engineers use lifetime curves published by manufacturers to verify that their system design meets the required reliability. An important condition for the lifetime of a module under repeated temperature swings is the control strategy applied during the test. Power cycling tests with identical start condition but different control strategies have been performed, which have been conducted on specially assembled test equipment with ultimate control of all test parameters. The results show, that different control strategies deliver lifetime results that vary by a factor of 3.

Impact of absolute junction temperature on power cycling lifetime

The influence of the absolute junction temperature Tj* on IGBT power module lifetime was systematically investigated by means of active power cycling tests. Both the impact on the wire bond lift-off and the chip solder degradation mechanism could be determined separately by applying the concept of separating failure modes. The test results not only prove that classical lifetime models overestimate the influence of Tj*, but also show that the two dominant failure mechanisms have to be treated differently. The wire bond lift-off failure mode is weakly affected by the absolute temperature level and possesses a very small activation energy of 0.069 eV. The solder degradation mode exhibits a significantly larger activation energy of 0.159 eV, which results in a massive decrease (factor 3) in power cycling capability when increasing Tj* by 85 K. For junction temperatures above 175°C SnAg-based solder joints are no longer suitable for reliable power module designs and advanced die attach technologies such as silver sintering have to be deployed. For the description of such advanced power modules specific lifetime curves are under development which exclusively represent the pure wire bond lifetime, as for common power cycling conditions the silver sintered die attach is not subjected to ageing.

Using the Chip as a Temperature Sensor - The Influence of Steep Lateral Temperature Gradients on the VCE(T)-Measurement

During operation steep lateral temperature gradients evolve in IGBT power semiconductor chips. The influence of these lateral gradients on the measurement of the virtual junction temperature by means of the widely used VCE(T)-method was investigated. In particular we address the question, how the obtained single temperature value is connected to the temperature distribution of the chip. A combination of electrical and thermal measurements together with thermal simulations was performed to understand the implicit averaging mechanisms of the VCE(T)-measurement. It is found that the lateral temperature gradient in the chip results in an inhomogeneous sense current distribution during the measurement. This current distribution is responsible for the formation of the measurement value and its corresponding temperature T∗. A comparison of experimental and simulation results shows that for currently existing IGBTs, T∗ corresponds to the area-weighted average of the chips active area. The maximum imbalance in sense current density during the VCE(T)-measurement was determined to be 150% and 50% of the average current density for the central and the corner parts of the chip, respectively. Furthermore, the temporal evolution of the temperature profile and its influence on the thermal impedance measurement are discussed. It is shown that the temperature at the chip center evolves with a smaller thermal time constant (i.e. faster evolution) than at the chip corners.

Power Semiconductor Devices – Key Components for Efficient Electrical Energy Conversion Systems

In a competitive market, technical systems rely on automation and process control to improve their productivity. Initially, these productivity gains were focused on attaining higher production volumes or less (human) labor-intensive processes to save costs. Today, attention is paid toward energy efficiency because of a global awareness of climate change and, above all, questions related to increasing energy prices, as well as security of energy and increasing urbanization. Consequently, it is expected that the trend toward more electrical systems will continue and accelerate over the next decades. As a result, the need to efficiently process electrical energy will dramatically increase.

Power Device-Induced Oscillations and Electromagnetic Disturbances

Every power electronic switching action results in a deviation from the ideal sinusoidal AC current or the ideal homogeneous DC current. Switching events are usually done periodically in time. Every periodic event can be separated into a row of sinus and cosinus terms by means of Fourier transformation. With this tool, the generated frequencies, the harmonics, and their intensity can be calculated.

Power Electronic Systems

The expression “power electronic system” is used in different contexts with different meanings. A monograph on fundamental power electronic circuittopologies might well be found under the search criterion ‘systems.’ It is therefore appropriate to start with a precise definition of the object of discussion.

Impact of load pulse duration on power cycling lifetime of chip interconnection solder joints

Abstract Thermo-mechanical stress limits the useful life of power modules in the application. Active power cycling tests have been applied for more than three decades to investigate the degradation generated by thermo-mechanical stress in accelerated testing. Different lifetime models were proposed to extrapolate the lifetime from accelerated test results to application conditions. However, these lifetime models did not differentiate between the prominent failure mechanisms of Al wire bond degradation and solder fatigue in classical modules. By combining new, highly reliable interconnection technologies with classical technologies, those failure mechanisms can be investigated separately. In previous publications this concept of separation of failure modes was applied to study the impact of temperature swing and medium temperature on each failure mode in power cycling. In the present study, the impact of power pulse duration on the lifetime of chip solder and Al wire bonds is investigated. The results are another jigsaw piece for the goal of proposing a lifetime model for chip solder interconnections. The empirical data base is furthermore indispensable for the scaling and validation of physic-of-failure approaches in the process of lifetime modelling.

Packaging and Reliability of Power Devices

The operation of a power semiconductor device produces dissipation losses. The order of magnitude of these losses shall be estimated in the following example:

Destructive Mechanisms in Power Devices

This chapter will deal with some destructive mechanisms in power devices, and typical failure pictures for them will be shown. Failure analysis requires a lot of experience, especially regarding the conditions in the power circuit at failure, which must be carefully considered. Although some of the failure pictures appear to be similar, it is difficult to draw conclusions only from pictures. However in practice the engineer often has the problem to find the reason for failures, and the following sections might be helpful.