V. Ferlet-Cavrois

Radiation Effects in MOS Oxides

Electronic devices in space environments can contain numerous types of oxides and insulators. Ionizing radiation can induce significant charge buildup in these oxides and insulators leading to device degradation and failure. Electrons and protons in space can lead to radiation-induced total-dose effects. The two primary types of radiation-induced charge are oxide-trapped charge and interface-trap charge. These charges can cause large radiation-induced threshold voltage shifts and increases in leakage currents. Two alternate dielectrics that have been investigated for replacing silicon dioxide are hafnium oxides and reoxidized nitrided oxides (RNO). For advanced technologies, which may employ alternate dielectrics, radiation-induced voltage shifts in these insulators may be negligible. Radiation-induced charge buildup in parasitic field oxides and in SOI buried oxides can also lead to device degradation and failure. Indeed, for advanced commercial technologies, the total-dose hardness of ICs is normally dominated by radiation-induced charge buildup in either parasitic field oxides and/or SOI buried oxides. Heavy ions in space can also degrade the oxides in electronic devices through several different mechanisms including single-event gate rupture, reduction in device lifetime, and large voltage shifts in power MOSFETs.

Radiation effects in SOI technologies

Silicon-on-insulator (SOI) technologies have been developed for radiation-hardened applications for many years and are rapidly becoming a main-stream commercial technology. The authors review the total dose, single-event effects, and dose rate hardness of SOI devices. The total dose response of SOI devices is more complex than for bulk-silicon devices due to the buried oxide. Radiation-induced trapped charge in the buried oxide can increase the leakage current of partially depleted transistors and decrease the threshold voltage and increase the leakage current of fully depleted transistors. Process techniques that reduce the net amount of radiation-induced positive charge trapped in the buried oxide and device design techniques that mitigate the effects of trapped charge in the buried oxide have been developed to harden SOI devices to bulk-silicon device levels. The sensitive volume for charge collection in SOI technologies is much smaller than for bulk-silicon devices potentially making SOI devices much harder to single-event upset (SEU). However, bipolar amplification caused by floating body effects can significantly reduce the SEU hardness of SOI devices. Body ties are used to reduce floating body effects and improve SEU hardness. SOI ICs are completely immune to classic four-layer p-n-p-n single-event latchup; however, floating body effects make SOI ICs susceptible to single-event snapback (single transistor latch). The sensitive volume for dose rate effects is typically two orders of magnitude lower for SOI devices than for bulk-silicon devices. By using body ties to reduce bipolar amplification, much higher dose rate upset levels can be achieved for SOI devices than for bulk-silicon devices.

Statistical Analysis of the Charge Collected in SOI and Bulk Devices Under Heavy lon and Proton Irradiation—Implications for Digital SETs

The statistical transient response of floating body SOI and bulk devices is measured under proton and heavy ion irradiation. The influence of the device architecture is analyzed in detail for several generations of technologies, from 0.25 mum to 70nm. The effects of the measured transients on SET sensitivity are investigated. The amount of collected charge and the shape of the transient currents are shown to have a significant impact on the temporal width of propagating transients. Finally, based on our measured data, the threshold LET and the critical transient width for unattenuated propagation are calculated for both bulk and floating body SOI as a function of technology scaling. We show that the threshold LETs and the critical transient widths for bulk and floating body SOI devices are similar. Body ties can be used to harden SOI ICs to digital SET. However, the primary advantage of SOI technologies, even with a floating body design, mostly lies in shorter transients, at a given ion LET, for SOI technologies than for bulk technologies

Single Event Transients in Digital CMOS—A Review

The creation of soft errors due to the propagation of single event transients (SETs) is a significant reliability challenge in modern CMOS logic. SET concerns continue to be exacerbated by Moores Law technology scaling. This paper presents a review of digital single event transient research, including: a brief historical overview of the emergence of SET phenomena, a review of the present understanding of SET mechanisms, a review of the state-of-the-art in SET testing and modelling, a discussion of mitigation techniques, and a discussion of the impact of technology scaling trends on future SET significance.

Direct measurement of transient pulses induced by laser and heavy ion irradiation in deca-nanometer devices

This paper investigates the transient response of 50-nm gate length fully and partially depleted SOI and bulk devices to pulsed laser and heavy ion microbeam irradiations. The measured transient signals on 50-nm fully depleted devices are very short, and the collected charge is small compared to older 0.25-/spl mu/m generation SOI and bulk devices. We analyze in detail the influence of the SOI architecture (fully or partially depleted) on the pulse duration and the amount of bipolar amplification. For bulk devices, the doping engineering is shown to have large effects on the duration of the transient signals and on the charge collection efficiency.

Comparison of charge yield in MOS devices for different radiation sources

NMOS transistors were irradiated using X-ray, Co-60 gamma, electron, and proton radiation sources. The charge yield was estimated for protons of different energies and electrons and compared to values obtained for X-ray and Co-60 irradiations.

Effects of particle energy on proton-induced single-event latchup

The effect of proton energy on single-event latchup (SEL) in present-day SRAMs is investigated over a wide range of proton energies and temperature. SRAMs from five different vendors were irradiated at proton energies from 20 to 500 MeV and at temperatures of 25/spl deg/ and 85/spl deg/C. For the SRAMs and radiation conditions examined in this work, proton energy SEL thresholds varied from as low as 20 MeV to as high as 490MeV. To gain insight into the observed effects, the heavy-ion SEL linear energy transfer (LET) thresholds of the SRAMs were measured and compared to high-energy transport calculations of proton interactions with different materials. For some SRAMs that showed proton-induced SEL, the heavy-ion SEL threshold LET was as high as 25MeV-cm/sup 2//mg. Proton interactions with Si cannot generate nuclear recoils with LETs this large. Our nuclear scattering calculations suggest that the nuclear recoils are generated by proton interactions with tungsten. Tungsten plugs are commonly used in most high-density ICs fabricated today, including SRAMs. These results demonstrate that for system applications where latchups cannot be tolerated, SEL hardness assurance testing should be performed at a proton energy at least as high as the highest proton energy present in the system environment. Moreover, the best procedure to ensure that ICs will be latchup free in proton environments may be to use a heavy-ion source with LETs /spl ges/40 MeV-cm/sup 2//mg.

Impact of Heavy Ion Energy and Nuclear Interactions on Single-Event Upset and Latchup in Integrated Circuits

The effects of heavy ion energy and nuclear interactions on the single-event upset (SEU) and single-event latchup (SEL) response of commercial and radiation-hardened CMOS ICs are explored. Above the threshold LET for direct ionization-induced upsets, little difference is observed in single-event upset and latchup cross sections measured using low versus high energy heavy ions. However, significant differences between low- and high-energy heavy ion test results are observed below the threshold LET for single-node direct ionization-induced upsets. The data suggest that secondary particles produced by nuclear interactions play a role in determining the SEU and SEL hardness of integrated circuits, especially at low LET. The role of nuclear interactions and implications for radiation hardness assurance and rate prediction are discussed.

Total Ionizing Dose Effects on Triple-Gate FETs

This paper investigates the total ionizing dose response of advanced nonplanar triple-gate transistors with short gate length, as a function of device geometry. Experiments and three-dimensional (3-D) simulations using a radiation dedicated code are used to analyze the buildup of a trapped charge in the buried oxide and its impact on the device electrical characteristics. The behaviors of three prospective nonplanar devices are detailed and compared to the total ionizing dose degradation of a planar fully depleted single-gate architecture. The Omega-gate FET is shown to be the most tolerant to a 500 krad(SiO2) total dose exposure thanks to the efficient control provided by the lateral gates over the electrostatic potential throughout the Si film and essentially at the Si fin/BOX interface

Total ionizing dose effects on deca-nanometer fully depleted SOI devices

Total ionizing dose effects are investigated for the first time in deca-nanometer fully depleted (FD) silicon-on-insulator (SOI) devices. Charge trapping and the influence of device architecture are investigated in transistors with and without external body contacts. A radiation-induced high current regime is measured in floating body devices, both at high and low drain voltages. The mechanism responsible for the onset of this high current regime is investigated by 2D numerical simulations, and shown to result from the combined effect of short gate length and floating body potential in the intrinsic Si film. Transistors with a doped Si film are less sensitive to the high current regime. The use of external body contact in the device architecture completely stops the onset of high current regime, whatever the device gate length.