Marta Bagatin

A New Hardware/Software Platform and a New 1/E Neutron Source for Soft Error Studies: Testing FPGAs at the ISIS Facility

We introduce a new hardware/software platform for testing SRAM-based FPGAs under heavy-ion and neutron beams, capable of tracing the bit-flips in the configuration memory back to the physical resources affected in the FPGA. The validation was performed using, for the first time, the neutron source at the RAL-ISIS facility. The ISIS beam features a 1/E spectrum, which is similar to the terrestrial one with an acceleration between 107 and 108 in the energy range 10-100 MeV. The results gathered on Xilinx SRAM-based FPGAs are discussed in terms of cross section and circuit-level modifications.

Radiation Effects in Flash Memories

We review ionizing radiation effects in Flash memories, the current dominant technology in the commercial non-volatile memory market. A comprehensive discussion of total dose and single event effects results is presented, concerning both floating gate cells and peripheral circuitry. The latest developments, including new findings on the mechanism underlying upsets due to heavy ions and destructive events, are illustrated.

TID Sensitivity of NAND Flash Memory Building Blocks

NAND Flash memories are the leader among high capacity non-volatile memory technologies and are becoming attractive also for radiation harsh environments, such as space. For these applications, a careful assessment of their sensitivity to radiation is needed. In this contribution, we analyze TID effects on the many different building blocks of NAND Flash memories, including the charge pumps, row-decoder, and floating gate array. Since each of these elements have dedicated circuital and technological characteristics, we identify and study the characteristic failure mode for each part.

Error Instability in Floating Gate Flash Memories Exposed to TID

We discuss new experimental results on the post-radiation annealing of Floating Gate errors in Flash memories with both NAND and NOR architecture. We investigate the dependence of annealing on the program level, linking the reduction in the number of Floating Gate errors to the evolution of the threshold voltage of each single cell. To understand the underlying physics we also discuss how temperature affects the number of Floating Gate errors.

Key Contributions to the Cross Section of NAND Flash Memories Irradiated With Heavy Ions

Heavy-ion irradiation of NAND flash memories under operating conditions leads to errors with complex, data-dependent signatures. We present upsets due to hits in the floating gate array and in the peripheral circuitry, discussing their peculiarities in terms of pattern dependence and annealing. We also illustrate single event functional interruptions, which lead to errors during erase and program operations. To account for all the phenomena we observe during and after irradiation, we propose an ldquoeffective cross section,rdquo which takes into account the array and peripheral circuitry contributions to the SEU sensitivity, as well as the operating conditions.

Catastrophic Failure in Highly Scaled Commercial NAND Flash Memories

Heavy ion single-event measurements on a variety of high density commercial NAND flash memories are reported. Three single event effect (SEE) phenomena were investigated: single effect upsets (SEUs), single effect functional interrupts (SEFIs), and a new high current phenomenon which at high LETs results in catastrophic loss of ability to erase and program the device.

Heavy-Ion Induced Threshold Voltage Tails in Floating Gate Arrays

We studied heavy-ion effects on floating gate memories, focusing on the generation of tails in the threshold voltage distributions after irradiation. Using both experiments and simulations based on the Geant4 toolkit, we provide new insight, distinguishing two types of events, large events and small events, which are responsible for the secondary peak and the intermediate region in the post-rad threshold distribution, respectively. Both are well correlated with the energy deposited in the FG. Implications for error rate predictions are discussed.

Annealing of Heavy-Ion Induced Floating Gate Errors: LET and Feature Size Dependence

We discuss the room temperature annealing of Floating Gate errors in Flash memories with NAND and NOR architecture after heavy-ion irradiation. We present the evolution of raw bit errors as a function of time after the exposure, examining the annealing dependence on the particle LET, cell feature size, and, for Multi Level Cells, on the program level. The results are explained based on the statistical properties of the cell threshold voltage distributions before and after heavy-ion strikes.

Impact of NBTI Aging on the Single-Event Upset of SRAM Cells

We analyzed the impact of negative bias temperature instability (NBTI) on the single-event upset rate of SRAM cells through experiments and SPICE simulations. We performed critical charge simulations introducing different degradation patterns in the cells, in three technology nodes, from 180 to 90 nm. The simulations results were checked with α-particle and heavy-ion irradiations on a 130-nm technology. Both simulations and experimental results show that NBTI degradation does not significantly affect the single-event upset SRAM cell rate as long as the parametric drift induced by aging is within 10%.

Increase in the Heavy-Ion Upset Cross Section of Floating Gate Cells Previously Exposed to TID

Electronic chips working in the space environment are constantly subject to both single event and total ionizing dose effects. To emulate this scenario for Flash memories, we tested under heavy ions floating gate cells, previously irradiated with x-rays, without performing any erase and program operation in between the two exposures. We observed an increase in the heavy-ion upset cross section in the devices that were submitted to TID irradiations, especially at low LETs. This effect is attributed to the combination of the threshold voltage shifts induced by heavy ions and x-rays. Implications for the hardness assurance of Flash memories are discussed.