V. P. Shmerko

Functional entropy and decision trees

We introduce a technique to compute several information estimations for Boolean and multivalued functions. Special features of these estimations for completely and incompletely specified logic functions, including symmetric logic functions are investigated. Finally, we give an algorithm for determining various information measures for logical functions based on decision trees.

Design of neuromorphic logic networks and fault-tolerant computing

This paper studies robust fault-tolerant neuromorphic computing to support enabling application-specific design and enable emerging nanoscaled microelectronics. We develop an energy-centric probabilistic design concept and propose a library of neuromorphic networks for logic functions. These developments enable robustness, failure tolerance capabilities, adaptation and reconfiguration of complex large-scale networks. The proposed methods and tools in design of neuromorphic networks are verified for unreliable, defective, faulty and failed interconnect and cells which may operate under large perturbations.

Linear Models of Circuits Based on the Multivalued Components

Linearization and planarization of the circuit models is pivotal to the submicron technologies. On the other hand, the characteristics of the VLSI circuits can be sometimes improved by using the multivalued components. It was shown that any ℓ-level circuit based on the multivalued components is representable as an algebraic model based on ℓ linear arithmetic polynomials mapped correspondingly into ℓ decision diagrams that are linear and planar by nature. Complexity of representing a circuit as the linear decision diagram was estimated as O(G) with G for the number of multivalued components in the circuit. The results of testing the LinearDesignMV algorithm on circuits of more than 8000 LGSynth 93 multivalued components were presented.

Design of nanoelectronic ICs: Noise-tolerant logic based on cyclic BDD

This paper reports new and practical design schemes for nanoscale integrated circuits, in order to ensure their functionality despite noise and faults. The proposed designs use a new cyclic binary decision diagram (BDD). The cyclic BDD enables the conventional BDD design algorithms by using feedback and Markov Random Field (MRF) model of logic gates. By applying the feedback and MRF premises, effective and robust design can be achieved. Simulations are reported to justify the fault-tolerance and noise-immunity of the proposed schemes.

Introduction to Noise-Resilient Computing

Abstract Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MR...