Tamer Mohamed

Integrated hardware-software platform for image processing applications

This paper illustrates the design and implementation of an integrated hardware-software platform for image processing. This platform is versatile as it is configurable at run time, has low power consumption and requires minimal processing power from the host. Thus, the illustrated solution makes complex multimedia processing tasks feasible on handheld devices with low processing power and limited battery life. The concept is illustrated by a prototype system for image compression. The hardware part is an FPGA board that can be plugged into a standard PCMCIA socket on any portable system. The FPGA is configured at run time to perform block discrete cosine transforms (DCT). The software part running on the host computer is responsible for configuring the device at run time and sending chunks of input data and getting back the computed results. The design was tested successfully and performs 8*8 block DCT in 64 clock cycles running at 60MHz. An alternative hardware-efficient design using distributed arithmetic was also considered. The complete hardware/software prototype was integrated as a part of MPEG-4 encoder software.

A hardware-accelerated framework with IP-blocks for application in MPEG-4

In this paper we present a hardware-accelerated framework and hardware blocks for MPEG-4 part 10 IP-quality assessment. We give examples of various IP-blocks that have been designed and tested on the integration platform. The hardware-accelerated framework enabled us to asses their quality along with the MPEG-4 part 10 software reference model.

Introduction to Noise-Resilient Computing

Abstract Noise abatement is the key problem of small-scaled circuit design. New computational paradigms are needed -- as these circuits shrink, they become very vulnerable to noise and soft errors. In this lecture, we present a probabilistic computation framework for improving the resiliency of logic gates and circuits under random conditions induced by voltage or current fluctuation. Among many probabilistic techniques for modeling such devices, only a few models satisfy the requirements of efficient hardware implementation -- specifically, Boltzman machines and Markov Random Field (MRF) models. These models have similar built-in noise-immunity characteristics based on feedback mechanisms. In probabilistic models, the values 0 and 1 of logic functions are replaced by degrees of beliefs that these values occur. An appropriate metric for degree of belief is probability. We discuss various approaches for noise-resilient logic gate design, and propose a novel design taxonomy based on implementation of the MR...

A rapid. prototyping framework for MPEG/H.264-enabled consumer products

The work presents a hardware-software API that is introduced by MPEG-4 part 9. The proposed rapid prototyping platform accelerates the development and deployment of hardware accelerated MPEG/H.264 enabled devices. This project focuses on the rapid prototyping and implementation of a system-on-chip MPEG-4 video encoder/decoder. This chip can be used as an added coprocessor to give the capabilities of video broadcasting or conferencing to available portable devices. The developed framework; on top of the rapid prototyping platform, provides a hardware layer that can host off-the-shelf ip-cores for video processing. The results of this project were proposed to the 2004 MPEG (Mohamed, T.S. and Badawy, W., ISO/IEC JTC1/SC29/WG11/m 10439, 2003; ISO/IEC JTC1/SC29/WG11/m 10824, 2004).

On the design flow of a hardware/software platform for MPEG-4 part 9 reference hardware model

This paper illustrates the design and implementation of an integrated hardware-software platform for image processing. This platform is versatile as it is configurable at run time. This platform is configured to act as a co-processor for the main processor of a host personal computer such that a complex computational task is moved to hardware and the processing on part of the host computer is reduced to just data communication with the co-processor. Thus, the proposed solution makes complex multimedia processing tasks feasible on handheld devices with low processing power and limited battery life. The concept is illustrated by a prototype system for image compression. The hardware part is an FPGA board that can be plugged into a standard PCMCIA socket on any portable system. The FPGA is configured at run time to perform the two most computationally extensive tasks in MPEG-4; namely; motion estimation and discrete cosine transform. The complete hardware/software prototype was integrated as a part of MPEG-4 encoder software. The measured results indicate that the overall system speed is independent of the speed of the processor of the host computer. The hardware part design is based on systolic architectures and satisfzes better than real time performance with low power consumption. Index Terms Hardware/software integration, Multimedia, MPEG-4, Discrete cosine transform, Motion Estimation.

Motion estimation architecture for mpeg-4 part 9: reference hardware description

This paper presents part of University of Calgary contribution in developing BO/IEC JTCl/SC29/WG Il/N5370 as part of the MPEG-4 Part 9: Reference Hardware Description. The main objective of that project is to design a System-on-Chip platform for MPEG-4 applications. The designed modules will be implemented on Annapolis Wildcard II. New motion estimation architecture is presented in this paper. This module replaces the motion estimation software module in the MPEG-4 encoder to assist the MPEG-4 software to achieve the required real-time constrains. The proposed architecture processes one CIF video pame in 8.712 ms using 93 MHz clock frequency. Therefore, it can process up to 114 CIF video frames per second. Index Terms Hardwarehoftware integration, Multimedia, MPEG-4. Motion Estimation.

Hybrid Simulation Environment for Construction Projects: Identification of System Design Criteria

Large construction projects are complex, dynamic, and unpredictable. They are subject to external and uncontrollable events that affect their schedule and financial outcomes. Project managers take decisions along the lifecycle of the projects to align with projects objectives. These decisions are data dependent where data change over time. Simulation-based modeling and experimentation of such dynamic environment are a challenge. Modeling of large projects or multiprojects is difficult and impractical for standalone computers. This paper presents the criteria required in a simulation environment suitable for modeling large and complex systems such as construction projects to support their lifecycle management. Also presented is a platform that encompasses the identified criteria. The objective of the platform is to facilitate and simplify the simulation and modeling process and enable the inclusion of complexity in simulation models.

On using FPGAS to accelerate the emulation of quantum computing

This paper investigates the possibility of implementing a conventional computing architecture that can practically emulate the functionality of a hypothetical quantum computer. The state of the art transistor feature size makes the resource requirement, for emulating quantum computation with a relatively large number of qubits, possible. In this paperwe investigate how a programmable logic array can be used to practically emulate quantum computation with entanglement characteristics. We illustrate the concept of our practical quantum computer emulator by examining the steps required to build a HW/SW co-design system that can automatically instantiate HW components that implement a quantum computing processing step.

Crossbar latch-based combinational and sequential logic for nano FPGA

Molecular based devices exhibit favorable electrical characteristics that make them candidates for implementing digital electronic circuits at the nanoscale. Previous work focused on using the crossbar array to implement programmable logic arrays in which hybrid CMOS/nano approaches rely on lithographic scale electronics for signal restoration and inversion. In this paper, the crossbar latch, which is an integral part of the crossbar array, is used to implement full combinational logic circuits with signal restoration and inversion. Nano architectures of primary combinational and sequential building blocks are presented since they constitute the basis of a homogeneously structured nanoprocessor or nano FPGA. The presented nano system interacts with lithographic devices only for programming and signal I/O.

Boolean Logic Circuits on Nanowire Networks and Related Technologies

Implementation of graph-based logic circuits on semiconductor nanowire networks and related technologies are described. Boolean logic function is graphically represented utilizing a binary decision diagram (BDD), unlike the conventional logic circuit in which a logic gate has a specific function as a logic operator. Logical graph structure is topologically transferred to a semiconductor nanowire network structure. BDD 2-bit arithmetic logic unit (ALU) is demonstrated on a GaAs-based regular nanowire network with hexagonal topology. A reconfigurable BDD logic circuit based on Shannon’s expansion of Boolean logic function and Fault-tolerant BDD on the basis of an error-correcting technique are also described.