V. Ya. Stenin

Simulation of the characteristics of the DICE 28-nm CMOS cells in unsteady states caused by the effect of single nuclear particles

Trigger transistors of the DICE CMOS memory cell can be divided into two groups and spaced topologically; and if the effect of single nuclear particle affects transistors of only one group, no upset of the cell state occurs, while the cell transforms into the unsteady state. If transistors of the second group are simultaneously affected, and this effect exceeds the threshold one, then the upset of the initial state occurs. If the effect on the second group is lower than the threshold one, then the cell returns to the initial steady state from an unsteady one. Characteristics of the DICE CMOS memory cell with a 28-nm design rule are simulated and analyzed for unsteady states caused by the influence of a single nuclear particle on transistors of only one or both groups of cell transistors.

Modeling the characteristics of trigger elements of two-phase CMOS logic, taking into account the charge sharing effect under exposure to single nuclear particles

The fault tolerance of CMOS D and RS flip-flops with a two-phase structure and memory cells based on them under exposure to single nuclear particles depends on the response to charge collection by several nodes. The relation between pairs of nodes with identical critical characteristics and specifics of symmetry of electric couplings between trigger transistors was established for DICE and Quatro cells. Critical pairs of nodes with minimal critical charges and an increased noise immunity were determined. The guidelines for mutual arrangement of transistors in DICE cells were given. The examples of quantitative estimation of critical dependences were given for cells with a 65 nm bulk CMOS design rule. DICE cells have an advantage in the event of multiple influence on the nodes.

CMOS logic elements with increased failure resistance to single-event upsets

Two-phase submicron CMOS logic elements with a design standard of 0.18 μm are analyzed that are based on two symmetric signal transfer and conversion logical channels (phases). The basic elements of two-phase CMOS logic are 2- and 4-transistor CMOS converters that form two-phase inverters, NAND elements, and D and RS triggers. Two-phase CMOS inverters based on 2-transistor converters with transversely connected inputs and elements based on these inverters, NAND elements and D and RS triggers also with transversely connected constituent elements, are the best ones with respect to the set of parameters, including the failure resistance to single-event upsets (with respect to the value of the critical switching charge), size, and switching time. The values of the critical switching charges of the elements of two-phase CMOS logic under exposure to individual nuclear particles that induce ionization currents with fall-time constants (diffusion component) from 0.3 ns to 2.0 ns are determined.

Prospects for using submicron CMOS VLSI in fault-tolerant equipment operating under exposure to atmospheric neutrons

Single-event upsets and latchups, whose removal is the subject of designing fault- tolerant VLSI and VLSI-based equipment, are the main effects of VLSI exposure to atmospheric neutrons. For a comparative analysis of the fault tolerance of CMOS structures with various design standards, we have investigated domestic and foreign CMOS VLSI with design standards from 0.5 to 0.13 μm and additionally produced test structures of submicron SRAMs with design standards of 0.5, 0.35, and 0.18 μm. The SOI CMOS technology provides the highest efficiency among the design-technological methods. There are no latchups in the specimens of test structures with design standards of 0.5 and 0.35 μm exposed to 250-MeV and 1-GeV protons. We recommend developing the basic components of submicron VLSI with an enhanced resistance to atmospheric neutrons based on techniques that include the typical SEU cross sections and the thyristor- effect cross sections obtained here for CMOS VLSI with various design standards.

Memory-cell layout as a factor in the single-event-upset susceptibility of submicron dice CMOS SRAM

Computer simulations with the Spectre circuit simulator from Cadence Design Systems and a proton-accelerator experiment are conducted to investigate the relationship of single-event-upset (SEU) susceptibility to memory-cell layout in the context of a 0.18-μm CMOS SRAM using the dual interlocked storage cell (DICE) technology with differing separations of the pair transistors designed to store a 0 or 1, namely, 0.9 and 2.5 μm, respectively. The simulated values of critical charge for an upset are found to be greater by a factor of 10 for the wider separation. With 1-GeV proton irradiation, using the wider separation of pair transistors is found to reduce the SEU count by a factor of 5.5–15 (depending on the supply voltage). In the experiment, lowering the supply voltage of the memory bank from 1.8 to 0.7 V is found to increase on average the SEU cross section by a factor of 3. Close agreement is observed between the simulated and measured results.

Basic memory elements using DICE cells for fault-tolerant 28 nm CMOS RAM

A CMOS DICE (Dual Interlocked Storage Cell) cell consists of two transistor groups whose layout on the crystal increases the cell’s stability against the impact of single nuclear particles. A fault of the cell’s state does not take place if the particle impacts transistors of one group only. The topological layouts of basic memory elements with a different relative position of two transistor groups of 28 nm CMOS DICE cells were designed and analyzed. Different cell layouts with a distance between the sensitive pairs of transistors of two groups of 1, 2, and 3 µm and a set of basic memory elements for designing memory arrays of static RAM with increased stability with respect to state faults due to the particle track charge separation between two transistor groups of the cell were proposed. The area of the DICE cells is larger by a factor of 2.1–2.5 than that of sixtransistor cells with transistors of the same size.

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

The first experimental test of new DICE memory cells with the transistors spaced into two groups (Spaced Transistor Groups DICE—STG DICE), composed on a 65-nm CMOS static RAM proved their high upset resilience. The STG DICE memory cells have two communication wires between the two groups of transistors that made it possible to use the striping of groups of transistors to increase the distances between sensitive nodes of cells up to 2.32–3.09 μm at a small increase in cell area. The blocks of 65-nm 128 × 32-bit CMOS RAM cache and 32 × 64-bit multiport RAM based on the STG DICE cells are characterized by upset thresholds lying in the range of 3.55–4.05 nJ of the laser pulse energy with a pulse duration of 70 ps and diameter of the spot of 3.5 μm. These threshold values exceed the upset thresholds of 65-nm CMOS RAM on 6T memory cells by factors of 20 for RAM cache and 3.5 for multiport RAM. In STG DICE RAM multiple upsets are absent in contrast to RAM based on 6T-cells.

Features of design of submicron CMOS of Static RAMs with an increased failure resistance to the effect of high-energy particles

The results of the comparative investigation of CMOS memory cells with a 0.18-μm design rule showed that the best parameters both in terms of their failure resistance to the effects of the influence of separate high-energy particles and in terms of sizes and speed are inherent to the DICE (Dual Interlocked Storage Cell) memory cells. According to the results of the design of single-ported and dual-ported 0.18-μm CMOS RAM units, based on DICE memory cells and with the use of constructive measures of protection from the thyristor effects, specifically, contacts to the substrate and n-pockets and guard rings, the coefficients of consumption of the crystal area for the banks of memory cells, units of control logic, interconnections, and RAM supply ring are substantiated. The increase in the RAM area is not larger than by a factor of 1.7–2.7, with the conservation of speed and increase in supplied consumption by a factor of 1.4–2.0 for RAM with a capacity of up to 128 Kbit; for a RAM capacity of 1 Mbit, the coefficient of the increase in area is 3.1, with the provision of the maximum failure resistance for the static RAM by bulk CMOS technology with a 0.18-μm design rule.

Simulation of the local effect of nuclear particles on 65-nm CMOS elements of two-phase logics

The influence of capacitive couplings of the buses connecting differential parts of two-phase CMOS logic elements with a 65-nm design rule on the failure sensitivity of elements due to the effect of separate nuclear particles is simulated. The sensitivity characteristics of two-phase inverters, NAND elements, trigger cells, and controlling elements of RS and D triggers is determined. The effects of the separate nuclear particle were simulated by current pulses with the rise time constant of 10 ps and fall time constants of 30 ps and 300 ps. The admissible values of capacitances of inputs of differential parts of two-phase CMOS logic elements of 0.3...0.7 fF are established depending on the element type and its logic state. The critical charges for two-phase logic elements are 32–88 fC, which is better by a factor of 10–15 than for elements with the conventional CMOS circuit technology with the same 65-nm design rule.

Simulation of Single Event Effects in STG DICE Memory Cells

TCAD simulation of single event effects in memory cells with transistors spaced into two groups (spaced transistor groups—STG DICE) is carried out on the set of test tracks passing through the drains of mutually sensitive CMOS transistors from one group and between the two groups at depths of 50–850 nm from the chip surface. When the charge from the track affects only one group of transistors, no upsets occur; in this case, the duration of the unsteady state is described by a linear function with a coefficient of 1.3–2.4 ps/(MeV cm2/mg) for tracks 50–350 nm deep and a coefficient of 11–12 ps/(MeV cm2/mg) for tracks 450–850 nm deep, with the linear energy transfer on the tracks ranging from 1 to 60 MeV cm2/mg in both cases. An upset of the logical state of the STG DICE cell can occur when the particle tracks follow the line connecting the two groups of transistors and when angular deviations from it are in the range of 40°. With the track normal to the chip surface, an upset can occur when the linear energy transfer exceeds 50–60 MeV cm2/mg.