Pavel Stepanov

Modeling the characteristics of trigger elements of two-phase CMOS logic, taking into account the charge sharing effect under exposure to single nuclear particles

The fault tolerance of CMOS D and RS flip-flops with a two-phase structure and memory cells based on them under exposure to single nuclear particles depends on the response to charge collection by several nodes. The relation between pairs of nodes with identical critical characteristics and specifics of symmetry of electric couplings between trigger transistors was established for DICE and Quatro cells. Critical pairs of nodes with minimal critical charges and an increased noise immunity were determined. The guidelines for mutual arrangement of transistors in DICE cells were given. The examples of quantitative estimation of critical dependences were given for cells with a 65 nm bulk CMOS design rule. DICE cells have an advantage in the event of multiple influence on the nodes.

Basic memory elements using DICE cells for fault-tolerant 28 nm CMOS RAM

A CMOS DICE (Dual Interlocked Storage Cell) cell consists of two transistor groups whose layout on the crystal increases the cell’s stability against the impact of single nuclear particles. A fault of the cell’s state does not take place if the particle impacts transistors of one group only. The topological layouts of basic memory elements with a different relative position of two transistor groups of 28 nm CMOS DICE cells were designed and analyzed. Different cell layouts with a distance between the sensitive pairs of transistors of two groups of 1, 2, and 3 µm and a set of basic memory elements for designing memory arrays of static RAM with increased stability with respect to state faults due to the particle track charge separation between two transistor groups of the cell were proposed. The area of the DICE cells is larger by a factor of 2.1–2.5 than that of sixtransistor cells with transistors of the same size.

Upset-resilient RAM on STG DICE memory elements with the spaced transistors into two groups

The first experimental test of new DICE memory cells with the transistors spaced into two groups (Spaced Transistor Groups DICE—STG DICE), composed on a 65-nm CMOS static RAM proved their high upset resilience. The STG DICE memory cells have two communication wires between the two groups of transistors that made it possible to use the striping of groups of transistors to increase the distances between sensitive nodes of cells up to 2.32–3.09 μm at a small increase in cell area. The blocks of 65-nm 128 × 32-bit CMOS RAM cache and 32 × 64-bit multiport RAM based on the STG DICE cells are characterized by upset thresholds lying in the range of 3.55–4.05 nJ of the laser pulse energy with a pulse duration of 70 ps and diameter of the spot of 3.5 μm. These threshold values exceed the upset thresholds of 65-nm CMOS RAM on 6T memory cells by factors of 20 for RAM cache and 3.5 for multiport RAM. In STG DICE RAM multiple upsets are absent in contrast to RAM based on 6T-cells.

Design of logical elements for the 65-nm CMOS translation lookaside buffer with compensation of single events effects

Logical elements for translation lookaside buffers were designed with single-event compensations and simulated on the bulk 65-nm CMOS design rule. The effects of upsets and single-event transients under impacts of single nuclear particles on MOS logical elements were minimized by the hardening the design. The basis of the fault-tolerant design is the hardened main row elements of the common matrix in arrays of Content-Addressable Memory (CAM) cells and RAM cells. The basis of the coincidence logic of CAM is combinational logic elements with the single-event compensation using masking and compensation.

Probabilistic modelling processes of mutual monitoring operators actions for transport systems

The research quantitatively proved, that the popular today the mode for estimating risks in operators actions based on uses of exponential probability distribution function (PDF) of time between mistakes of operators is a rough and unpromising engineering way. Its application deforms very essentially probabilistic estimations of risks. Operator may be a man or special device or their combination. For systems, composed from mutual monitoring operators, deviations of risks may be about hundreds and thousands of percent. The more adequate approach for probabilistic modelling processes for is proposed, including intelligent transportation systems, oil&gas transportation systems, infrastructure etc. The logic structure of operators (as a system) and details of threats, system control, possibilities of mutual monitoring and recovery time for every operator are considered. The results are useful for understanding mutual monitoring effects and rationale of counteraction measures against different “human factor” affects. Effects are demonstrated by examples.

Simulation of the local effect of nuclear particles on 65-nm CMOS DICE memory cells

Sensitivity characteristics of the DICE CMOS memory cells as two-phase D triggers with the 65-nm design rule. The dependences of critical values of the amplitudes of current pulses causing the failures during recording and storing the data are determined for various coupling capacitances of differential inputs of two-phase inverters in the composition of the memory cell. The following limitations for the values of these capacitances are established: 0.4–0.5 fF for memory cells based on NMOS transistors with a channel width of 400 nm and 0.2–0.3 fF for NMOS transistors with a channel width of 120 nm. Evaluations of critical integral charges that characterize the failure tolerance under the effect of separate nuclear particles give correspondingly values of 25–20 fC, which is larger by a factor of 8 compared with the 6-transistor CMOS memory cells.

The static RAM on DICE cells spaced onto two groups

Static RAM with a traditional topology of DICE designed by scaling with rules less than 65-nm lost advantages in failure tolerance to single nuclear particles compared to CMOS RAM on 6-T memory cells. Transistors of the STG DICE cell have been separated onto two groups so that impact of single nuclear particles on one of the groups do not lead to an upset of the logic state of the cell, but only causes a transient effect. Spacing and interleaving of several groups enables the maximum distances between the mutually sensitive nodes of the two groups of transistors of STG DICE. In this case, the area of the layer of active devices may be equal to the area of the layer of metallization in the basic memory elements. It allowed increasing the distance between mutually sensitive nodes of each of DICE cells to values more than 2 μm. This approach ensured the increase of additional area of the DICE cell 15 % only. Static cache RAMs as parts of the microprocessor system in bulk CMOS 65 nm technology were tested for the upset immunity using the laser pulse technique.