Vadim V. Ivanov

A Sub-1-V Low-Noise Bandgap Voltage Reference

A new sub-1-V bandgap voltage reference is presented in this paper, which has advantages over the prior arts in terms of output noise and compatibility with several fabrication processes. The topology allows the reference to operate with a supply voltage as low as 1 V by employing the reverse bandgap voltage principle (RBVP). It also has an attractive low-noise output without the use of a large external filtering capacitor. The design was fabricated with a 0.5-mum BiCMOS process, but it is compatible with most CMOS and BiCMOS fabrication processes. The entire die area is approximately 0.4 mm2, including all test pads and dummy devices. Theoretical analysis and experimental results show that the output noise spectral density is 40 nV/radicHz with a bias current of 20 muA. Moreover, the peak-to-peak output noise in the 0.1-10 Hz band is only 4 muV. The untrimmed reference has a mean output voltage of 190.9 mV at room temperature, and it has a temperature coefficient in the -40degC to +125degC range of 11 ppm/degC (mean) with a standard deviation of 5 ppm/degC.

A 330nA energy-harvesting charger with battery management for solar and thermoelectric energy harvesting

Harvesting energy from ambient energy sources such as solar and thermal gradients is one solution to address the dramatic increase in energy consumption of personal electronics. In this paper, an ultra low quiescent current charger and battery management IC that can efficiently extract energy from solar panels and thermoelectric generators to charge batteries and super capacitors is presented. While previous works on energy harvesting [1-5] report efficient DC-DC converters to extract the energy from the harvester, not all of them provide complete battery management functionality for various chemistries. Also, maximum power point tracking (MPPT) which is critical in energy harvesting applications is not provided in some of the published work. In this paper, a charger and battery management IC with 330nA quiescent current is presented. The IC can cold start from 330mV and 5μW of input power. The charger achieves efficiency greater than 80% at single cell solar voltages of 0.5V. A low quiescent current battery management architecture involving sampled circuits, sub regulated rails and clock gating is demonstrated.

An Ultra Low Power Bandgap Operational at Supply From 0.75 V

We present an ultra low power (200 nA current consumption) reverse bandgap voltage reference operational from supply voltages down to 0.75 V. The reference is a part of microprocessor system on chip implemented in a digital 130 nm CMOS process and has a total area of 0.07 mm2. The reference accuracy is ± 2.5% (5 sigma) over a temperature range of - 20 to 85°C without trimming. With trimming ± 0.5% accuracy is achieved.

A CMOS bandgap voltage reference with absolute value and temperature drift trims

We present a curvature-corrected CMOS bandgap voltage reference with in-package trim of the absolute value and first-order temperature drift during the final test. The trim settings are stored using a poly fuse ROM. The output buffer has a single-stage topology with voltage and current gain boosts, providing 20 /spl mu/V/mA load regulation and frequency stability with any load. The total error of the voltage reference, implemented in the TSMC 0.6 /spl mu/m process, does not exceed 200 ppm in the full temperature (-40/spl deg/C to 125/spl deg/C), supply (1.8 V to 5.5 V) and load (/spl plusmn/10 mA) range.

A Sub-i V Low-Noise Bandgap Voltage Reference

A new sub-1-V bandgap voltage reference is presented in this paper, which has advantages over the prior arts in terms of output noise and compatibility with several fabrication processes. The topology allows the reference to operate with a supply voltage as low as 1 V by employing the reverse bandgap voltage principle (RBVP). It also has an attractive low-noise output without the use of a large external filtering capacitor. The design was fabricated with a 0.5-mum BiCMOS process, but it is compatible with most CMOS and BiCMOS fabrication processes. The entire die area is approximately 0.4 mm2, including all test pads and dummy devices. Theoretical analysis and experimental results show that the output noise spectral density is 40 nV/radicHz with a bias current of 20 muA. Moreover, the peak-to-peak output noise in the 0.1-10 Hz band is only 4 muV. The untrimmed reference has a mean output voltage of 190.9 mV at room temperature, and it has a temperature coefficient in the -40degC to +125degC range of 11 ppm/degC (mean) with a standard deviation of 5 ppm/degC.

Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation and Low Noise

Application of the structural methodology to the LDO design creates a new class of circuits: any load stable, with instant transient response, large power supply rejection and low noise. Presented are examples of the embedded in SoC LDOs for the SRAM unit (5 ns reaction time on the load steps), radio transmitter (shaping the required noise vs. frequency curve) and for memory retention in the shutdown state (300 nA quiescent current). These LDOs can operate with or without off-chip load capacitors; they are robust to the process and temperature variations and portable to any CMOS process.

A 100-dB CMRR CMOS Operational Amplifier With Single-Supply Capability

A CMOS operational amplifier that has a common-mode rejection ratio (CMRR), a power-supply rejection ratio (PSRR), and gain above 100 dB for each of these parameters is described. This is achieved by combining a high output-impedance tail current source with a stable drain-source voltage of the input transistors. The common-mode input signal range includes the negative rail. This is obtained by controlling the bulk bias of the input and cascoding transistors. The amplifier consists of two gain stages connected via cascoded current mirrors. The gain is improved by using gain boost in the current mirrors, and by the suppression of impact ionization current in the output stage

Bandgap voltage references with 1V supply

The structure, operation principle and set of circuit implementations of the low output voltage (~200 mV) bandgap voltage references are presented. References are capable for operating with a supply below 1V, while having accuracy and noise parameters comparable with the traditional 1.2 V bandgap reference. References core can use substrate, lateral or vertical PNP or NPN transistors, which allows implementation on almost any process. A test reference fabricated with the 50HPA07 BiCMOS process from Texas Instruments shows untrimmed output voltages with less than 1% production scattering (3sigma). The temperature coefficient is below 20 ppm/degC while minimum supply voltage is 1 V at -40 to 125degC range

Structural Design of a CMOS Full Low Dropout Voltage Regulator

The paper describes structural design of a full (complete) low dropout (LDO) voltage regulator. This LDO is using the following basic subcircuits: bandgap reference (BGR), folded-cascode current operational amplifier (COA), and bias circuit. The regulator is divided in three main blocks, namely, a sub-regulator generating power supply voltage for the BGR, a scaling amplifier providing convenient reference voltage for the LDO, and the LDO itself providing the required output voltage. Each block is consisting of a COA, pass transistor and resistor and represents a dedicated feedback loop. The regulator does not require any on-chip compensation capacitors, and ensures stable operation for a very wide range of capacitive loads. The complete LDO regulator is realized in standard digital 0.13-mum CMOS process for the output voltage of 1.22 V from 1.8-3.3 V power supply.

An ultra low power bandgap operational at supply as low as 0.75V

We present an ultra low power (200nA consumption) reverse bandgap voltage reference operational from supply voltages as low as 0.75V. The reference is a part of a microcontroller system and has total area of 0.07 mm² implemented in a digital 130 nm CMOS process. Accuracy of ±1.5% (5 sigma) over temperature range −20 to 85°C without trimming and ±0.5% with trimming is achieved.