Frank Vanselow
Texas Instruments
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Publication
Featured researches published by Frank Vanselow.
european solid-state circuits conference | 2013
Stefan Dietrich; Lei Liao; Frank Vanselow; Ralf Wunderlich; Stefan Heinen
The output voltage ripple is one of the most significant system parameters in switch-mode power supplies. This ripple degrades the performance of application specific integrated circuits (ASICs). The most common way to reduce it is to use additional integrated low drop-out regulators (LDO) on the ASIC. This technique usually suffers from high system efficiency as it is required for portable electronic systems. It also increases the design challenges of on-chip power management circuits and area required for the LDOs. This work presents a low-power fully integrated 0.97mm2 DC-DC Buck converter with a tuned series LDO with 1mV voltage ripple in a 0.25μm BiCMOS process. The converter prodives a power supply rejection ratio of more than 60 dB from 1 to 6MHz and a load current range of 0...400 mA. A peak efficiency of 93.7% has been measured. For high light load efficiency, automatic mode operation is implemented. To decrease the form factor and costs, the external components count has been reduced to a single inductor of 1 μH and two external capacitors of 2 μF each.
ieee international newcas conference | 2012
Stefan Dietrich; Harald Sandner; Frank Vanselow; Ralf Wunderlich; Stefan Heinen
Modelling of system components gains more and more interest in the design flow of integrated analog circuits. Digital parts are well described using e.g. Matlab Simulink or VHDL. On the other hand, analog circuits are complex to model and, therefore, its modeling is time consuming due to missing simulation speed-up or accuracy. Nevertheless, as system complexity rises and transistor level simulations nearly become impossible, adequate models of large integrated analog circuits, like DC-DC converters, are essential. This paper deals with a practical solution to model an integrated, hysteretic controlled DC-DC buck converter. The well known Texas Instruments TPS 62620 is used as an example. The consistency between the modelled chip and the datasheet is shown, while a simulation speed-up of about 30 has been achieved.
Archive | 2007
Frank Vanselow; Chung San Roger Chan
Archive | 2008
Thomas Refeld; Frank Vanselow
Archive | 2008
Frank Vanselow; Matthias Arnold
Archive | 2002
Frank Vanselow; Leonardo Curradi
Archive | 2006
Roger Chan; Frank Vanselow
Archive | 2010
Vadim V. Ivanov; Juergen Neuhaeusler; Frank Vanselow
Archive | 2007
Matthias Arnold; Frank Vanselow
Archive | 2006
Frank Vanselow