Valentin Rosskopf

Device architecture and process for improved vertical memory arrays

Integrated circuit configuration for testing transistors, and a semiconductor wafer having such a circuit configuration

Transistor array and semiconductor memory configuration fabricated with the transistor array

Semiconductor wafer with test structure

Test structure for determining a doping region of an electrode connection between a trench capacitor and a selection transistor in a memory cell array

Method for fabricating and checking structures of electronic circuits in a semiconductor substrate

Kerf with improved fill routine

Test structure for measuring a junction resistance in a DRAM memory cell array

Test structure for determining a short circuit between trench capacitors in a memory cell array

Semiconductor product having a semiconductor substrate and a test structure and method