Valluri Rao

Novel optical probing technique for flip chip packaged microprocessors

A novel infrared (IR) optical probing technique which provides fast and direct access to diffusion (p-n junction) nodes directly through the silicon substrate is described. The optical probing technology allows waveform measurements to be obtained directly from internal nodes of a CMOS integrated circuit (IC). These measurements can be made on C4 (Flip Chip) mounted ICs in stand-alone, MCM or any other package type for which the chip backside is accessible and the silicon substrate can be thinned. Timing waveforms taken from state of the art Intel microprocessors running at core frequencies >400 MHz using this IR probing technique have been obtained and are presented.

Laser voltage probe (LVP): a novel optical probing technology for flip-chip packaged microprocessors

A novel optical probing technique to measure voltage waveforms from flip-chip packaged CMOS integrated circuits (IC) is described. This IR laser based technique allows signal waveform acquisition and high frequency timing measurements directly from active P-N junctions through the silicon backside substrate on ICs mounted in flip-chip stand-alone or multi-chip module packages as well as wire-bond packages on which the chip backside is accessible. The technique significantly improves silicon debug and failure analysis (FA) throughput time (TPT) as compared to backside electron-beam (e-beam) probing because of the elimination of backside trenching and probe hole generation operations.

Metal contact reliability of RF MEMS switches

It is well-recognized that MEMS switches, compared to their more traditional solid state counterparts, have several important advantages for wireless communications. These include superior linearity, low insertion loss and high isolation. Indeed, many potential applications have been investigated such as Tx/Rx antenna switching, frequency band selection, tunable matching networks for PA and antenna, tunable filters, and antenna reconfiguration. However, none of these applications have been materialized in high volume products to a large extent because of reliability concerns, particularly those related to the metal contacts. The subject of the metal contact in a switch was studied extensively in the history of developing miniaturized switches, such as the reed switches for telecommunication applications. While such studies are highly relevant, they do not address the issues encountered in the sub 100μN, low contact force regime in which most MEMS switches operate. At such low forces, the contact resistance is extremely sensitive to even a trace amount of contamination on the contact surfaces. Significant work was done to develop wafer cleaning processes and storage techniques for maintaining the cleanliness. To preserve contact cleanliness over the switch service lifetime, several hermetic packaging technologies were developed and their effectiveness in protecting the contacts from contamination was examined. The contact reliability is also very much influenced by the contact metal selection. When pure Au, a relatively soft metal, was used as the contact material, significant stiction problems occurred when clean switches were cycled in an N2 environment. In addition, various mechanical damages occurred after extended switching cycling tests. Harder metals, while more resistant to deformation and stiction, are more sensitive to chemical reactions, particularly oxidation. They also lead to higher contact resistance because of their lower electrical conductivity and smaller real contact areas at a given contact force. Contact reliability issues could also be tackled by improving mechanical designs. A novel collapsing switch capable of generating large contact forces (>300μN) was shown to be less vulnerable to contamination and stiction.

Application of advanced micromachining techniques for the characterization and debug of high performance microprocessors

Micromachining techniques such as focused ion beam milling have become an integral part of the design debug cycle at many companies for providing fast verification of bug fixes in silicon. With flip chip packaging becoming more prevalent for future high performance processors, it is necessary to perform circuit edits and bug fixes on the silicon while the chip is packaged in the flip chip package. With this technology, however, conventional frontside probing and traditional circuit rewiring of packaged devices are not practical. We have developed a combination of new micromachining techniques for directly accessing metal signals from the backside of the chip. Here we will describe this new process, the technologies used, and some basic applications.

An ultraclean tip-wear reduction scheme for ultrahigh density scanning probe-based data storage.

Probe-based memory devices using ferroelectric media have the potential to achieve ultrahigh data-storage densities under high write-read speeds. However, the high-speed scanning operations over a device lifetime of 5-10 years, which corresponds to a probe tip sliding distance of 5-10 km, can cause the probe tip to mechanically wear, critically affecting its write-read resolution. Here, we show that the long distance tip-wear endurance issue can be resolved by introducing a thin water layer at the tip-media interface-thin enough to form a liquid crystal. By modulating the force at the tip-surface contact, this water crystal layer can act as a viscoelastic material which reduces the stress level on atomic bonds taking part in the wear process. Under our optimized environment, a platinum-iridium probe tip can retain its write-read resolution over 5 km of sliding at a 5 mm/s velocity on a smooth ferroelectric film. We also demonstrate a 3.6 Tbit/inch(2) storage density over a 1 × 1 μm(2) area, which is the highest density ever written on ferroelectric films over such a large area.

Scanning probe charge reading of ferroelectric domains

A scanning probe charge-detection technique based on direct piezoelectric effect is demonstrated to read alternating bit polarizations in a ferroelectric media The bit signal is generated by spatially modulating charges interacting with a probe tip scanning in contact with the media. A periodicity of the bits is used with an appropriate scan speed to modulate the signal frequency. A signal-to-noise ratio of 10 dB has been achieved for a contact force of 100 nN. The modulation of the bit signal frequency into the 2 kHz data rate is achieved by coupling 0.4 μm spacing between alternating polarizations with scanning speed of 1.6 mm/s.

Sputtered A1N Thin Films for Piezoelectric MEMS Devices

Piezoelectric films have been demonstrated to be attractive for micromechanical systems (MEMS) devices. Among the piezoelectric films used, AlN film has been less explored. In this study, AlN resonators and accelerometers, utilizing longitudinal and transverse piezoelectric effects respectively, were demonstrated. Resonators with Q of 1000 and electromechanical coupling (kt 2) of 6.5% were achieved at ~2 GHz. Accelerometers were fabricated and tested with charge sensitivities ranging between 0.06 to 0.45 pC/g depending on device designs. Important material properties of sputtered AlN films - C33 of 435 GPa, e33 of 1.55 C/m2, and e31 of -0.58 C/m2 - were extracted by fitting finite element analysis (FEA) simulated values to measured results.

Experimental observation and physics of “negative” capacitance and steeper than 40mV/decade subthreshold swing in Al 0.83 In 0.17 N/AlN/GaN MOS-HEMT on SiC substrate

GaN is a promising material for LED lighting [1], high voltage power electronics [2] and high power RF applications [3]. GaN HEMT and MOS-HEMT with AlGaN [4] or AlInN [5] polarization layer have been widely studied. In this work we investigate the effects of Al_0.83In_0.17N polarization layer thickness scaling on the device characteristics of Al_0.83In_0.17N/AlN/GaN MOS-HEMTs on SiC substrates. We have experimentally observed “negative” capacitance and subthreshold swing (SS) steeper than 40 mV/dec in GaN MOS-HEMTs with thin Al_0.83In_0.17N polarization layer, where composition modulation of Al% and In% is observed.

Novel optical probing and micromachining techniques for silicon debug of flip chip packaged microprocessors

Methods and techniques for micromachining and probing C4 packaged microprocessors from the silicon backside are described. The micromachining technique is based on using a combination of Laser Chemical Etching and Focused Ion Beam milling to open precision probe holes and perform circuit editing from the backside. A method to optically probe flip chip packaged CMOS microprocessors is also described. The optical probing technique utilizes an infrared laser to probe diffusions directly through the silicon backside without the need to mill probe holes.

Tuning the Built-in Electric Field in Ferroelectric Pb(Zr0.2Ti0.8)O3 Films for Long-Term Stability of Single-Digit Nanometer Inverted Domains

The emergence of new technologies, such as whole genome sequencing systems, which generate a large amount of data, is requiring ultrahigh storage capacities. Due to their compactness and low power consumption, probe-based memory devices using Pb(Zr(0.2)Ti(0.8))O(3) (PZT) ferroelectric films are the ideal candidate for such applications where portability is desired. To achieve ultrahigh (>1 Tbit/in(2)) storage densities, sub-10 nm inverted domains are required. However, such domains remain unstable and can invert back to their original polarization due to the effects of an antiparallel built-in electric field in the PZT film, domain-wall, and depolarization energies. Here, we show that the built-in electric-field can be tuned and suppressed by repetitive hydrogen and oxygen plasma treatments. Such treatments trigger reversible Pb reduction/oxidation activity, which alters the electrochemistry of the Pb overlayer and compensates for charges induced by the Pb vacancies. This tuning mechanism is used to demonstrate the writing of stable and equal size sub-4 nm domains in both up- and down-polarized PZT films, corresponding to eight inverted unit-cells. The bit sizes recorded here are the smallest ever achieved, which correspond to potential 60 Tbit/in(2) data storage densities.