Johanna M. Swan

Fabrication and electrical characterization of 3D vertical interconnects

3D die-stacking (Tanida et al, 2003; Hara et al, 2005) and wafer-stacking (Morrow et al, 2004) integration have recently been demonstrated using copper (Cu) interconnections and through silicon via technology. In 3D die-stacking approach, the Cu vertical interconnections are fabricated on the front-side of the silicon wafer along with the active circuitry followed by wafer thinning and die-stacking. The limitation of this approach is the impact to active circuitry from vertical interconnects processing. With the 3D wafer stacking approach, the wafers are bonded with the prefabricated active circuitry face-to-face prior to wafer thinning and Cu interconnects fabrication and inherently limit stack die configuration to matched die sizes. This approach has inherent benefits and limitations depend to a large extent on the targeted applications. In this paper, we present an alternate 3D die-stacking approach which involves wafer thinning prior to Cu interconnect fabrication in a silicon wafer consisting of pre-fabricated active circuitry. This approach allows for mixed die size and technology node integration in multi-chip packages while maximizing known good die yields. In this approach the electrical connection to the active circuitry is made through the Cu plated through-silicon via to large arrays of tungsten (W) contacts at the bulk silicon interface. The challenges in through-silicon via processing using this 3D die-stacking approach will be discussed. Backside processing impact to pre-fabricated transistors and fundamental RC performance of the through silicon via landing on contact will be presented

High-speed performance of Silicon Bridge die-to-die interconnects

Silicon Bridge is a dense multichip packaging architecture that enables high die-to-die interconnect density and corresponding applications. We describe the basic ideas of the concept, discuss density in the die-to-die interconnect context, and report results of electrical high-speed performance simulations, based on both two-dimensional and three-dimensional electromagnetic modeling.

Enhanced interfacial thermal transport in pnictogen tellurides metallized with a lead-free solder alloy

Controlling thermal transport across metal–thermoelectric interfaces is essential for realizing high efficiency solid-state refrigeration and waste-heat harvesting power generation devices. Here, the authors report that pnictogen chalcogenides metallized with bilayers of Sn96.5Ag3Cu0.5 solder and Ni barrier exhibit tenfold higher interfacial thermal conductance Γc than that obtained with In/Ni bilayer metallization. X-ray diffraction and x-ray spectroscopy indicate that reduced interdiffusion and diminution of interfacial SnTe formation due to Ni layer correlates with the higher Γc. Finite element modeling of thermoelectric coolers metallized with Sn96.5Ag3Cu0.5/Ni bilayers presages a temperature drop ΔT ∼ 22 K that is 40% higher than that obtained with In/Ni metallization. Our results underscore the importance of controlling chemical intermixing at solder–metal–thermoelectric interfaces to increase the effective figure of merit, and hence, the thermoelectric cooling efficiency. These findings should facilitate the design and development of lead-free metallization for pnictogen chalcogenide-based thermoelectrics.Controlling thermal transport across metal–thermoelectric interfaces is essential for realizing high efficiency solid-state refrigeration and waste-heat harvesting power generation devices. Here, the authors report that pnictogen chalcogenides metallized with bilayers of Sn96.5Ag3Cu0.5 solder and Ni barrier exhibit tenfold higher interfacial thermal conductance Γc than that obtained with In/Ni bilayer metallization. X-ray diffraction and x-ray spectroscopy indicate that reduced interdiffusion and diminution of interfacial SnTe formation due to Ni layer correlates with the higher Γc. Finite element modeling of thermoelectric coolers metallized with Sn96.5Ag3Cu0.5/Ni bilayers presages a temperature drop ΔT ∼ 22 K that is 40% higher than that obtained with In/Ni metallization. Our results underscore the importance of controlling chemical intermixing at solder–metal–thermoelectric interfaces to increase the effective figure of merit, and hence, the thermoelectric cooling efficiency. These findings should faci...

Active die embedded small form factor RF packages for ultrabooks and smartphones

This paper reports on the design, fabrication and characterization of active die embedded ultra slim system-in-packages suitable for integrating RF and digital integrated circuits, and discrete components. Portable communication devices such as Ultrabooks, tablets and smart phones require very small form factor radio subsystems. To address this need, several proof of concept (POC) packages with embedded active die have been designed and characterized. A 50% form factor reduction compared to packages currently used in radio system half minicards is achieved by using this packaging approach. Test results show that the radio frequency (RF) performance of this small form factor (SFF) SiP is within the system specification.

3D stacked embedded component system-in-package for wearable electronic devices

This paper discusses design, fabrication and characterization of a 3D stacked small form factor (SFF) system-in-packages (SiPs) suitable for wearable electronics systems. In order to achieve very small size SiP, two SFF multi-chip packages were designed and fabricated utilizing embedded wafer-level ball grid array (e-WLB) technology. The package consisted of six radio frequency (RF) and digital integrated circuits (ICs), and 24 passive components of varying sizes. 3-D stacked system in package was of size 6.0 × 5.5 × 1.9 mm and was 55% smaller than the same system fabricated using conventional printed circuit board technology. The measured results showed that system performance was on par with or better than the previous systems.

A Novel Technology for Creating Sensors and Actuators in Processor Packages

In this paper, a novel technology is presented in which organic substrate manufacturing is used to create sensors and actuators directly in the CPU package. The dielectric material surrounding some interconnect traces in the substrate is removed, allowing those traces to act as sensors and actuators, while the CPU itself is used for signal processing and conditioning. To demonstrate proof of concept, ultra-thin resonant accelerometers based on this approach are designed, manufactured, and successfully tested by using them to measure orientation changes. The approach realizes smart, compact package substrates with integrated sensing and actuation functionalities, thereby enabling a wide range of applications not previously feasible in CPU packages.

Engineering the effective CTE of Si die with a T2 package

With the continuous scaling of low k dielectric in multicore processors, the intrinsic CTE mismatch between a Si die (CTE: 2.3 ppm/°C) and an organic substrate (16-18 ppm/°C) brings a susceptibility for more failures. There are limited successes in the engineering of the CTE of substrate with ceramic (~6 ppm/°C) or low CTE organic substrates (~12 ppm/°C). The CTE mismatch also contributes to solder joint reliability risks and misalignment in assembly. In this paper, we propose a very different method to address the CTE mismatch: the effective CTE of Si is engineered to match that of an organic substrate instead. The T2 package with both thinner die and thinner thermal interface material (TIM) is proposed as both a mechanical and thermal solution for electronic packages. Experimental measurement using DIC (digital image correlation) shows that the effective CTE of silicon can be as high as 15-16 ppm/°C. Thus, it reduces the mismatch between the silicon die and the organic substrate from roughly 15 ppm/°C to 1-3 ppm/°C. Moiré measurement shows the corner stress reduction and the temperature cycle study proves the effectiveness of CTE engineering. Thermomechanical simulations and reliability studies with different Si die thicknesses are also reported.

An Overview of System in Package (SiP) Applications and Technologies for CPU and Communications Systems

Research and development on System in Package (SiP) technologies is prevalent now both in industry and academia. This paper provides an overview of SiP from a CPU and communications systems perspective. Some of the items that will be covered include what defines a “system” for SiP, what value a SiP architecture brings, the types of SiP packaging architectures and technologies, and the challenges involved with developing SiP solutions.Copyright