Vamsi Boppana

Full fault dictionary storage based on labeled tree encoding

The process of fault dictionary compaction can lead to a loss of information that is potentially useful in locating unmodeled failures. The focus of this paper is on developing alternative storage structures that can efficiently represent full fault dictionaries without discarding any information. We present the problem of storing the full fault dictionary storage as a labeled tree encoding problem. Two labeled trees are introduced to represent the diagnostic experiment. For the first tree, the unlabeled tree is stored using a binary string code, while the second tree is constructed so that the unlabeled tree is regular in structure, thus allowing implicit storage. Eight alternative representations based on the three label components are presented and two existing full fault dictionary representations (the matrix and the list dictionaries) are shown to be special cases in our general framework. Experimental results on the ISCAS 85 and ISCAS 89 circuits are used to study and characterize the performance of the proposed storage structures.

Diagnostic test pattern generation for sequential circuits

A method to perform diagnostic test generation in sequential circuits by modifying a conventional test generator is presented. The method utilizes circuit netlist modification along with a forced value at primary input in the modified circuit techniques to reduce the computational effort for diagnostic test pattern generation in sequential circuits. Speed-up of the diagnostic ATPG process is achieved by the identification of states that are impossible to justify with three-valued logic.

Diagnostic fault equivalence identification using redundancy information and structural analysis

A significant problem with current diagnostic test generation techniques is the time spent in identifying diagnostic equivalences amongst fault pairs. Fault pair distance analysis is introduced in this paper to characterize diagnostically equivalent fault pairs and motivate local circuit transformations and structural analysis to identify equivalences in combinational circuits rapidly. Our results establish a connection between redundant faults and a specific class of diagnostically equivalent fault pairs. Structural analysis is then used to identify equivalences between fault pairs. Experimental results are presented on benchmark circuits to demonstrate the efficiency of the techniques.

Fault equivalence identification using redundancy information and static and dynamic extraction

A procedure for identifying functionally equivalent faults and improving the performance of diagnostic test pattern generation is described in this paper. The procedure is based on evaluation of faulty functions in cones of dominator gates of fault pairs. This is enhanced by utilizing circuit redundancy information. Equivalence is proved without the previously required circuit transformations. Stem-branch equivalences for reconvergent stems and their branches are identified efficiently obviating the need to check for non-masking and multiple-path sensitization. Both static and dynamic techniques are developed to exploit relations among inputs of dominator cones. This reduces the simulation time required by the procedure and enables evaluation of larger cones than could be evaluated earlier. As a result, more equivalent fault pairs are identified. Experiments performed on ISCAS85 circuits and full scan ISCAS89 circuits are used to demonstrate the effectiveness of the proposed techniques.

Fault dictionary compaction by output sequence removal

Fault dictionary compaction has been accomplished in the past by removing responses on individual output pins for specific test vectors. In contrast to the previous work, we present techniques for eliminating entire sequences of outputs and for efficiently storing the remaining output sequences. Experimental results on the ISCAS 85 and ISCAS 89 benchmark circuits show that the sizes of dictionaries proposed are substantially smaller than the full fault dictionary, while the dictionaries retain most or all of the diagnostic capability of the full fault dictionary.

Partial scan design based on state transition modeling

Selection of flip-flops that provide the best improvements in testability is a critical part of the partial scan design process. This paper describes a new technique for flip-flop selection that models the effect of scan in terms of the introduction of pseudo state transitions in the state transition graph. The identification of (desired) state transitions that provide for improved testability is based on an analysis of the known reachable states and desired states which ensure improved fault detection. Experiments are presented on the ISCAS 89 circuits to show significant improvements in the testability of the resulting partial scan design.

Implication and evaluation techniques for proving fault equivalence

Efficient identification of fault equivalence is essential for the completeness and efficiency of diagnostic test pattern generation. In this paper, we present new techniques to prove diagnostic fault equivalence. The techniques are based on implication of the faulty values, and functional evaluation at the dominator gate of the fault sites. The experimental results for all ISCAS85 circuits and full scan versions of ISCAS89 circuits show significant improvement compared to previously proposed techniques in both the number of equivalent pairs identified and the time to prove equivalence.

Fault diagnosis using state information

Repeated fault diagnosis on large integrated circuits may often be computationally prohibitive due to expensive fault simulation requirements. Fault dictionaries can help alleviate this problem, but they may be infeasible to store because of their large sizes, and more importantly, they typically provide only a black box view of the circuit and hence almost no diagnostic flexibility. The problem occurs because dictionaries usually only store primary output information. A new approach to fault diagnosis based on state information is presented. The selective storage of state information is shown to significantly improve the time for diagnostic fault simulation. We also describe a method to reduce the amount of information stored by choosing only a subset of the state space. This approach is shown to be ideally suited for partial scan circuits whose simple structure is exploited to reduce storage requirements. Experiments on the ISCAS 89 benchmark circuits are performed to demonstrate the efficiency of the state information based diagnosis technique.

Characterization and implicit identification of sequential indistinguishability

Effective diagnosis of integrated circuits relies critically on the quality of diagnostic test vectors. Diagnostic test pattern generation aims at producing test vectors that distinguish between all distinguishable pairs of faults, and proving the remaining pairs of faults to be indistinguishable. Proving indistinguishabilities, much like proving undetectabilities in the case of detection-oriented test pattern generation, requires substantial computational effort. In this paper, we simplify the problem by showing that a significant number of indistinguishability relations can be proven implicitly, with little computational effort. Sequential indistinguishability is characterized and conditions for the identification of new indistinguishability relations based on already existing relations are established. Experiments on the ISCAS 89 benchmark circuits are presented to indicate the significant improvements achievable by the implicit identification of indistinguishabilities.

Identification of unsettable flip-flops for partial scan and faster ATPG

State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (hip-hops) that are either difficult to set or unsettable. This is achieved by performing test generation on certain transformed circuits to identify state elements that are not settable to specific logic values. Two applications that benefit from this identification are sequential circuit test generation and partial scan design. The knowledge of the state space is shown to be useful in creating early backtracks in deterministic test generation. Partial scan selection is also shown to benefit from the knowledge of the difficult-to-set hip-hops. Experiments on the ISCAS89 circuits are presented to show the reduction in time for test generation and the improvements in the testability of the resulting partial scan circuits.