W. Kent Fuchs

Efficient Spare Allocation for Reconfigurable Arrays

Yield degradation from physical failures in large memories and processor arrays is of significant concern to semiconductor manufacturers. One method of increasing the yield for iterated arrays of memory cells or processing elements is to incorporate spare rows and columns in the die or wafer. These spare rows and columns can then be programmed into the array. The authors discuss the use of CAD approaches to reconfigure such arrays. The complexity of optimal reconfiguration is shown to be NP-complete. The authors present two algorithms for spare allocation that are based on graph-theoretic analysis. The first uses a branch-and-bound approach with early screening based on bipartite graph matching. The second is an efficient polynomial time-approximation algorithm. In contrast to existing greedy and exhaustive search algorithms, these algorithms provide highly efficient and flexible reconfiguration analysis.

Fault dictionary compression and equivalence class computation for sequential circuits

A new technique for creating small fault dictionaries for sequential circuits is presented, along with a hybrid combination of that new technique with another and performance improvements for a previously published technique. Seven techniques are compared and evaluated by their impact on dictionary size, fault simulation costs, and diagnostic resolution losses. The comparisons show that compact dictionaries with full resolution are computationally expensive, while small, inexpensive dictionaries almost always suffer a resolution loss. Measures of diagnostic resolution are described with an algorithm to approximate them in linear time. Experiments are presented for the ISCAS sequential benchmark circuits.

Rapid Diagnostic Fault Simulation of Stuck-at Faults in Sequential Circuits using Compact Lists

This paper describes a diagnostic fault simulator for stuck-at faults in sequential circuits that is both time and space efficient. The simulator represents indistinguishable classes of faults as memory efficient lists. The use of lists reduces the number of output response comparisons between faults and hence speeds up the simulation process. The lists also make it easy to drop faults when they are fully distinguished from other faults. Experimental results on the ISCAS89 circuits show that the simulator runs significantly faster than an earlier work based on distinguishability matrices and is faster and more memory efficient than a recent method based on lists of indistinguishable faults. The paper provides the first reports on pessimistic and optimistic diagnostic measures for all faults of the large ISCAS circuits.

Reconfigurable cube-connected cycles architecture

Abstract In this paper two different approaches to designing reconfigurable cube-connected cycles parallel computation networks are proposed. Both architectures are capable of tolerating classes of multiple failures. The first approach is based on allocating spare processors and spare communication links in each cycle and utilizes local reconfiguration. The second approach is based on spare cycles (columns) and rows of processors and employs global reconfiguration techniques. Both of the approaches are shown to result in increases in reliability with reasonable increases in redundancy while maintaining many of the VLSI layout and implementation advantages of classical cube-connected cycles architectures.

Consistent global checkpoints based on direct dependency tracking

Abstract We model the consistent global checkpoints in a distributed system as the maximum-sized antichains in the partially ordered set generated by the happened before relation. While the partially ordered set generated by the direct dependency tracking in uncoordinated checkpointing protocols does not capture the complete happened before relation among all checkpoints, we show that the missing happened before information does not affect the identification of consistent global checkpoints.

Compiler-assisted full checkpointing

This paper describes a compiler‐based approach to checkpointing for process recovery. The implementation is transparent to both the programmer and the hardware. The compiler‐generated sparse potential checkpoint code maintains the desired checkpoint interval. Adaptive checkpointing reduces the size of the checkpoints. Training is used to select low‐cost, high‐coverage potential checkpoints. The problem of selecting potential checkpoints is shown to be NP‐complete, and a heuristic algorithm is introduced that determines a quick suboptimal solution. These compiler‐assisted checkpointing techniques have been implemented in a modified version of the GNU C (GCC) compiler. Experiments involving the modified version of the GCC compiler on a Sun SPARC workstation are summarized.

Partial scan design based on circuit state information

State information of a sequential circuit can be used to evaluate the complexity of test generation. The ratio of valid states to all the states of the circuit is an important indicator of test generation complexity. Using valid states obtained via logic simulation, a testability measure based on the density of encoding is proposed for scan flip flop selection. A second testability measure based on the test generation state information is also presented and used to select scan flip flops. Cycles are broken selectively on the basis of the circuit state information. Good fault coverage and test efficiency are obtained when fewer scan flip flops than the minimum cut set are selected. Experimental results are presented to demonstrate the effectiveness of the method.

Dynamic diagnosis of sequential circuits based on stuck-at faults

A dynamic diagnosis scheme for synchronous sequential circuits is proposed. In contrast with schemes like fault dictionaries no prior computation and storage of fault symptoms is performed. The technique combines cause-effect and effect-cause strategies. Cause-effect analysis is performed by single stuck at fault simulation followed by a matching algorithm. Effect-cause analysis is performed by an error propagation back-trace starting from the falling outputs. The error propagation back-trace eliminates from consideration faults that could not have caused the failing symptoms. The procedure is exact for defects behaving as single stuck-at faults. Experimental results are provided for the ISCAS89 benchmark circuits.

Fault dictionary compaction by output sequence removal

Fault dictionary compaction has been accomplished in the past by removing responses on individual output pins for specific test vectors. In contrast to the previous work, we present techniques for eliminating entire sequences of outputs and for efficiently storing the remaining output sequences. Experimental results on the ISCAS 85 and ISCAS 89 benchmark circuits show that the sizes of dictionaries proposed are substantially smaller than the full fault dictionary, while the dictionaries retain most or all of the diagnostic capability of the full fault dictionary.

Implementing Forward Recovery Using Checkpoints in Distributed Systems

This paper describes the implementation of a forward recovery strategy in a Sun NFS environment. The implementation is based on the concept of lookahead execution with rollback validation. It uses replicated tasks executing on different processors for forward recovery and checkpoint comparison for error detection. In the experiment described, the recovery strategy has nearly error-free execution time and an average redundancy lower than TMR.