Vandana Kumari

Two-Dimensional Analytical Drain Current Model for Double-Gate MOSFET Incorporating Dielectric Pocket

In this paper, a dielectric-pocket double-gate MOSFET is described for low-voltage low-power applications. A complete drain current model has been developed including the channel length modulation effect. The analytical results have been validated by comparing them with the simulation results using the ATLAS 3-D device simulator. This paper analyzes the impact of dielectric pillars on large-signal performance metrics in terms of linearity and digital performance. Due to high Ion/Ioff ratio, device gain, and extremely low value of intrinsic delay and power dissipation, the proposed design is a suitable candidate for low-voltage low-power digital and analog applications.

Analytical Modeling of Dielectric Pocket Double-Gate MOSFET Incorporating Hot-Carrier-Induced Interface Charges

In this paper, the impact of interface charges on the performance of a short-channel symmetric dielectric pocket double-gate (DP-DG) MOSFET has been investigated. An analytical drain current model for DP-DG MOSFET has been developed, which is also useful for investigating the impact of dual-material gate on DP-DG architecture. The proposed model is verified using ATLAS 3-D simulator. In addition, exhaustive simulation has been carried out to address the impact of interface charges on the reliability issues of various devices, i.e., DP-DG, double-gate, and dielectric pocket architectures in terms of gate leakage current, electron temperature, and impact of interface charges on the threshold voltage lowering. Analog and digital performances have also been investigated and compared with the other devices.

Theoretical Investigation of Dual Material Junctionless Double Gate Transistor for Analog and Digital Performance

In this paper, we report the 2-D drain current model for asymmetric dual material (DM) junctionless double gate transistor. On the basis of channel potential, transconductance and its higher order derivatives are estimated and verified with the ATLAS 3-D device simulator results. The developed model is also applicable to investigate the digital performance of the device in terms of voltage transfer characteristics of nMOS inverter circuit. The impact of the length of control gate on the analog performance has also been investigated. Results also highlight the advantage of DM gate over the single material gate for digital and analog applications using CMOS inverter and common source amplifier through exhaustive circuit simulation.

Nanoscale-RingFET: An Analytical Drain Current Model Including SCEs

In this paper, using a 2-D Poisson equation (in cylindrical coordinates), an analytical drain current model of a nanoscale RingFET architecture has been developed for the first time. Major short-channel effects, such as channel length modulation, velocity scattering, and drain-induced barrier lowering, are taken under consideration while developing the model. A bandgap narrowing model has been employed to investigate the impact of higher channel doping. The modeled results of the surface potential, electric field, threshold voltage (Vth), subthreshold slope, and drain current have been verified by comparing with those of the ATLAS 3-D device simulation. The influence of the drain radius and position of the source/drain regions on the electrical characteristics of the device has also been demonstrated.

Investigation of Electrostatic Integrity of Nanoscale Dual Material Gate Dielectric Pocket Silicon-on-Void (DMGDPSOV) MOSFET for Improved Device Scalability

This paper presents a 2-D temperature-dependent analytical drain current model, which is valid for six different device architectures (by slightly modifying the used parameters), i.e., dual material gate dielectric pocket silicon-on-void, dual material gate silicon-on-void, dual material gate silicon-on-insulator, dielectric pocket silicon-on-void, silicon-on-void, and silicon-on-insulator MOSFETs. The results thus obtained, i.e., drain current, transconductance, gm/Ids ratio, threshold voltage, subthreshold slope, and Ion/Ioff ratio have been verified with the simulated results obtained using ATLAS 3-D device simulator for channel length down to 30 nm. The analytical model is also used to investigate the impact of temperature variation on the characteristics of N-MOS inverter based on different architectures. In addition, impact of process and parameters variation (i.e., variation in shallow extension depth (Xe), side pillar thickness (Tst), thickness of buried oxide layer (t3) along with the variation in temperature) on the subthreshold performance of different devices has also been studied through exhaustive device simulation.

Investigation of Empty Space in Nanoscale Double Gate (ESDG) MOSFET for High Speed Digital Circuit Applications

The impact of Empty Space layer in the channel region of a Double Gate (i.e. ESDG) MOSFET has been studied, by monitoring the DC, RF as well as the digital performance of the device using ATLAS 3D device simulator. The influence of temperature variation on different devices, i.e. Double Gate incorporating Empty Space (ESDG), Empty Space in Silicon (ESS), Double Gate (DG) and Bulk MOSFET has also been studied. The electrical performance of scaled ESDG MOSFET shows high immunity against Short Channel Effects (SCEs) and temperature variations. The present work also includes the linearity performance study in terms of VIP2 and VIP3. The proper bias point to get the higher linearity along with the higher transconductance and device gain has also been discussed.

Performance Investigation of Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET for Low Volatge Digital Applications

The circuit level implementation of nanoscale Insulated Shallow Extension Silicon On Nothing (ISE-SON) MOSFET has been investigated and compared with the other conventional devices i.e. Insulated Shallow Extension (ISE) and Silicon On Nothing (SON) using the ATLAS 3D device simulator. It can be observed that ISE-SON based inverter shows better performance in terms of Voltage Transfer Characteristics, noise margin, switching current, inverter gain and propagation delay. The reliability issues of the various devices in terms of supply voltage, temperature and channel length variation has also been studied in the present work. Logic circuits (such as NAND and NOR gate) and ring oscillator are also implemented using different architectures to illustrate the capabilities of ISE-SON architecture for high speed logic circuits as compared to other devices. Results also illustrates that ISE-SON is much more temperature resistant than SON and ISE MOSFET. Hence, ISE-SON enables more aggressive device scaling for low-voltage applications.

Comparative Study of Silicon-on-Nothing and III–V-on-Nothing Architecture for High Speed and Low Power Analog and RF/Digital Applications

This paper investigates the impact of channel material engineering on the performance of silicon-on-nothing (SON) architecture for 32-nm technology node. The analog performance of SON architecture in terms of drive current Ids, transconductance (gm), early voltage Vea, trans-conductance generation efficiency gm/Ids, and output resistance Rout with different channel material, i.e., Si, SiGe, Ge, GaAs, and InP has been investigated by using ATLAS 3D device simulation. The impact of temperature variation on the analog performance of the device has also been studied. Due to high mobility channel material (i.e., for III-V-based MOSFET), device shows excellent performance for microwave application because of its high current gain (h21), unilateral power gain, and maximum available power gain Gma. Furthermore, the impact of high mobility channel material on the digital performance of the device has also been investigated by monitoring the CMOS inverter characteristics, i.e., voltage transfer characteristics and noise margin.

Sub-threshold Drain Current model of Double Gate RingFET (DG-RingFET) Architecture: An Analog and Linearity Performance Investigation for RFIC Design

ABSTRACT In the present work, impact of Double Gate RingFET (DG-RingFET) has been investigated for better gate control and suppressed Short Channel Effects (SCEs) using ATLAS 3D device simulator. The analog performance metrics explored in this paper are drain current (Ids − Vgs), trans-conductance (gm), device efficiency (gm/Ids), and early voltage (Vea). In addition to this linearity behaviour of DG-RingFET has been investigated in terms of third-order voltage intercept point (VIP3), third-order current intercept point (IIP3), third-order inter modulation distortion (IMD3) and results are also compared with the single gate architecture. The two-dimensional analytical model for DG-RingFET architecture has also been developed in this paper using parabolic approach. Moreover, the impact of technology variations like drain radii and position of drain, i.e. inside or outside the channel ring on the performance of DG-RingFET architecture has also been assessed.

Variability Investigation of Double Gate JunctionLess (DG-JL) Transistor for Circuit Design Perspective

Present work investigates the variability in the circuit performance of Double Gate JunctionLess (DG-JL) architecture due to variation in device parameters such as operating temperature (T), doping of the channel (Nch) and the variation in the doping profile (like Gaussian). We have also evaluated the impact of interface charges on the performance of DG-JL based CMOS inverter. Conventional CMOS inverter and amplifier circuit are used to demonstrate the performance of the DG-JL architecture. The parameters which are evaluated in this work are transfer characteristics, noise margin, propagation delay, inverter current and amplifier gain. Apart from this, influence of gate oxide permittivity on the transfer characteristics of CMOS inverter has been investigated. Presented results show that, the variation in the doping profile (i.e. from uniform to Gaussian) has lesser impact on the device performance. However, the change in peak doping concentration, operating temperature and influence of interface charges leads to significant change in inverter characteristics in terms of both noise margin and propagation delay.