Veepsa Bhatia

On improving the performance of Traff's comparator

In this paper a new current comparator is proposed which offers high speed and high resolution while maintaining low power dissipation. The design improves upon previous Traff current comparator by modifying the given gain stage which leads to up to 83% improvement in delay. Simulation results performed on SPICE using TSMC 0.18μm CMOS technology demonstrate that proposed current comparator has a resolution of ± 10nA and delay of 0.86ns at ± 1μA input current. Performance for lower supply voltages is also reported.

Delay area efficient low voltage FVF based current comparator

This paper presents an improved current comparator using flipped voltage follower (FVF) to obtain the single supply voltage. This circuit exhibits short propagation delay and occupies a small chip area. The proposed circuit has been simulated employing PSpice simulator for 0.18 μm CMOS technology and a comparison has been performed with its non FVF counterpart to contrast its effectiveness, simplicity, compactness and low power consumption.

Low power delay proficient current mode ADC design

Analog to Digital Converters (ADC) are one of the popular blocks in the area of mixed signal devices. This paper presents a circuit for 2-bit current-mode Flash ADC with very low propagation delay. The ADC employs high speed current comparator. Further, a high speed thermometer to binary CMOS pass gate encoder is implemented that exhibits an average delay of 0.25ns. The design which explicates 2-bit conversion can be expanded up to n-bits. The results assert the fact that there are no bubbles in the output. 0.18µm CMOS technology with 1.8V power supply voltage is used.

Performance comparison of an algorithmic current- mode ADC implemented using different current comparators

In this paper a 4-bit algorithmic current mode Analog-to-Digital Converter (ADC) has been implemented. A vital component of this ADC is a current comparator. We have simulated three popular structures of current comparators that can be used to implement this ADC and compared their performance. The circuit has been implemented using 0.18 µm CMOS technology with a supply voltage of 1.8V.

A 4-bit expandable algorithmic current-mode Analog to Digital Converter for use in digital control systems

In this paper a 4-bit expandable algorithmic Analog-to-Digital Converter has been implemented. It is based on current mode technique. The Analog-to-Digital Converter has been implemented for 4-bits here but can be easily expanded for higher number of bits using the algorithm presented here. The converter uses a current comparator. We have simulated two popular structures of current comparators that can be used to implement this Analog-to-digital Converter. The circuit has been implemented using 0.18 μm CMOS technology with a supply voltage of 1.8V.

Modified Tang and Punźs Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs

A modification to an existing current comparator proposed by Tang and Pun has been presented. The circuit introduces a flipped voltage follower (FVF) which replaces the source follower input stage of the existing current comparator of Tang and Pun. This modification culminates into higher speed especially at lower currents and lower power dissipation. The application of the proposed current comparator has also been put forth by implementing a 3-bit current mode (CM) ADC and a two-step 3-bit CM ADC. The theoretical propositions are verified through spice simulation using 0.18źźm TSMC CMOS technology at a power supply of 1.8źV. Propagation delay, power dissipation, and power delay product (PDP) have been calculated for the proposed current comparator and process parameter variation has been studied. For both the implementations of ADCs, performance parameters, namely, DNL, INL, missing codes, monotonicity, offset, and gain errors, have been evaluated.

Modelling a simple current to voltage converter using ANN

The transistor dimensions of devices in MOS based circuit highly influence the circuit characteristics and evaluation parameters. Choosing the dimensions while being critical is also extremely complex primarily due to complex mathematical formulations at the submicron level. Thus, it is required to employ techniques to simplify the dimensioning process while still keeping the parameters under check. This study presents one such novel technique to estimate the transistor dimensions for a current to voltage converter structure, using the artificial neural networks approach. The approach uses Multilayer perceptrons as the artificial neural network architectures. The technique involves a two-step process. In the first step, training and test data are obtained by doing SPICE simulations of modelled circuit using 0.18µm TSMC CMOS technology parameters. In the second step, this training and test data is applied to the developed neural network architecture using MATLAB R2007b.

A Novel Ultra Low Power Current Comparator

A novel ultra low power current comparator has been proposed in this paper. The current comparator utilizes Dynamic Threshold Metal Oxide Semiconductor (DTMOS) technique to reduce the power dissipation, by reducing the supply voltage. The circuit is capable of working at a supply voltage as low as ±0.2 V. The circuit has been implemented in 0.18 µm (Taiwan Semiconductos Manufacturing Company) TSMC technology parameters.

A novel CC-II based current comparator and its application as current mode flash ADC

In this paper, a new design for current comparator based on Current Conveyor-II (CC-II) is proposed. The proposed current comparator utilizes the concept of positive feedback. Simulations have been performed on Pspice using 0.18um CMOS technology with 1.8V supply. Final results confirm a fairly quick response, less power dissipation and a resolution of 4.4uA for the current comparator. A 2-bit current mode flash ADC is designed using the proposed comparator.

An expandable current-mode ADC with power optimization technique

A low delay and speed efficient current mode Analog to Digital Converter has been described. The Analog to digital converter architecture generates 4-bit digital output in two stages. Different current comparator architectures have been used in the design and for each, the effect on the speed and area of the Analog to digital converter has been determined. Further, a power optimization technique has been suggested to reduce dynamic power dissipation in the ADC. It has been designed using 0.18 μm CMOS technology and simulation results have been obtained using PSpice.