Venkatram Krishnaswamy

A study of bridging defect probabilities on a Pentium (TM) 4 CPU

Presents an experimental study of bridging fault locations on the Intel Pentium (TM) 4 CPU as determined by an inductive fault analysis tool. The study focuses on the location and distribution of probable bridging defects and attempts to explain the findings in the context of the characteristics of the design and its implementation. The coverage obtained against these faults by manually generated functional patterns is compared against that achieved by ATPG vectors.

Actor based parallel VHDL simulation using time warp

One of the methods used to reduce the time spent simulating VHDL designs is by parallelizing the simulation. In this paper, we describe the implementation of an object-oriented Time Warp simulator for VHDL on an actor based environment. The actor model of computation allows the exploitation of fine grained parallelism in a truly asynchronous manner and allows for the overlap of computation with communication. Some preliminary results obtained by simulating a set of multipliers and some ISCAS benchmark circuits are provided. In addition, the importance of placing processes based on circuit partitioning techniques for improving runtimes and scalability is demonstrated. Results are reported on a Sun SPARCServer 1000 and an Intel Paragon.

A switch level fault simulation environment

This paper presents a fault simulation environment which accepts pure switch level or mixed switch/RT level descriptions of the design under test. Switch level fault injection strategies for the stuck-at, transition and logic bridge models are presented. A fault simulation algorithm is presented, along with design issues and optimizations. The fault simulation algorithm places no restrictions on the circuit styles used to implement designs. Mixed level simulation issues are discussed. Fault simulation performance numbers on large industrial benchmarks are reported.

Automatic parallelization of compiled event driven VHDL simulation

In this paper, we present approaches and algorithms for parallelization of compiled event driven VHDL simulations on shared-memory multiprocessors (SMP). An efficient single-threaded algorithm for simulation of VHDL descriptions is first presented. This algorithm is shown to be competitive with a commercial VHDL simulator. Schemes for multithreaded execution of this algorithm are then described. These have been implemented on top of the POSIX pthreads library and experimental results have been shown on a Sun SparcServer 1000E. Speedups of up to four on eight processors have been achieved for some benchmarks.

Parallel compiled event driven VHDL simulation

This paper shows ways to speedup simulation of digital designs described in VHDL by executing them on parallel machines. An efficient sequential simulator based on compile time analysis is first described. Two approaches to parallelizing simulations are then shown. One is based on fine grain task scheduling, and the other on coarse-grain partitioning. Each has its domain of utility depending on the nature of the designs. Experimental results validate the different approaches.

Load balancing and work load minimization of overlapping parallel tasks

In this paper, we propose a unique problem in the assignment of overlapping tasks to processors on a parallel machine, with the twin objectives of minimizing workloads while maintaining good load balance. This problem arises in some applications in VLSI CAD, e.g. parallel compiled VHDL simulation. We assume that the parallel application can be decomposed into a set of tasks, each in turn comprising a finite number of subtasks. Overlapped computations arise as a result of replication of subtasks across tasks in order to reduce the amount of communication performed in fine grained parallel applications. The uniqueness of the problem stems from the fact that overlapping computation on tasks assigned to the same processor is only performed once. Theoretical results on NP-hardness and bounds on the utilization of overlap are provided. A heuristic solution is also proposed. An important application area in VLSI-CAD, parallel compiled event driven VHDL simulation is introduced. Results of the application of our heuristics to this problem are reported on a SUN Sparcserver 1000 multiprocessor.

A procedure for software synthesis from VHDL models

Addresses the problem of software generation from a hardware description language (HDL). In particular, we examine the issues involved in translating VHDL into C or C++ for use in system simulation and cosynthesis. Because of the concurrency supported by VHDL, and a notion of timing behavior, care must be taken to ensure behavioral correctness of the generated software. The issues involved are shown to be different in each of the application areas. The ideas set forth in this paper have been used in an efficient VHDL simulator designed to execute on multiprocessor systems. Results are presented for simulation on uniprocessor as well as multiprocessor systems.

Implications of VHDL timing models on simulation and software synthesis

Abstract In this paper, we address the timing semantics of the delay models handled by VHDL. A formal model is used to characterize the runtime work required to resolve multiple assignments to signals for each of these models. Subsets of these timing models which require minimal work at runtime for resolution of multiple assignments are identified. Algorithms for generation of efficient code for simulation and synthesis in these restricted timing models are given. We present runtimes of our implementation of a simulator which uses these algorithms.

Performance evaluation of message-driven parallel VLSI CAD applications on general purpose multiprocessors

This paper presents a detailed evaluation of parallel mesaagedriven pmgmms on both message-passing and shared memory pamllel architectures. Four large pomllel appiications from the domain of VLSI computer aided design are evaluated, namely: parallel test pattern genemtion, pamllel cell placement, logic qnthesis, and event dn’ven VHDL kmulalion. The parallelism structure, the communication characterktics, locality chamcterirrtics, gmin sizes of wmputationa, and detailed measurement8 of system time, idle time, and uaer time are meaaunzd for theae applicationa. Resulta are presented for an Intel Pamgon distributed-memory measagepassing multicomputer and compared to a Sun SPARCcenter 1 OOOE symmetric multiprocessor.

System modeling, performance analysis, and evolutionary prototyping with hardware description languages

Performance modeling, simulation and analysis of the system behavior through virtual prototyping, form the core steps of the system design process. Past CAD support to link the high level conceptual modeling phase with the implementation phase has been virtually non-existent. In this paper, we describe our work to use VHDL to build design libraries that support conceptual modeling. These library components can be instantiated for rapid prototyping, simulation, and performance analysis. They include high level structures to allow construction of system models containing both interpreted and uninterpreted components. This helps in creating a strong design environment in VHDL which can support the entire design cycle. In addition, the design libraries have been linked with a graphical design environment. This graphical environment provides a single framework in which the designer can (i) build the design, (ii) simulate the design for correctness, and (iii) visualize performance results and capacity measures.<<ETX>>