Dale E. Martin

WARPED: a time warp simulation kernel for analysis and application development

WARPED is a publically-available time warp simulation kernel for experimentation and application development. The kernel defines a standard interface to the application developer and is designed to provide a highly configurable environment for the integration of time warp optimizations. It is written in C++, uses the MPI (Message Passing Interface) standard and shared memory for communication, and executes on a variety of platforms including a network of SUN workstations, a SUN SMP workstation, the IBM SP1/SP2 multiprocessors, the Intel Paragon and IBM-compatible PCs running Linux. WARPED is distributed with several applications and includes a sequential kernel implementation for comparative analysis. The kernel supports LP (logical process) clustering, various time warp algorithms and several optimizations that dynamically adjust simulation parameters.

An Object-Oriented Time Warp Simulation Kernel

The design of a Time Warp simulation kernel is made difficult by the inherent complexity of the paradigm. Hence it becomes critical that the design of such complex simulation kernels follow established design principles such as object-oriented design so that the implementation is simple to modify and extend. In this paper, we present a compendium of our efforts in the design and development of an object-oriented Time Warp simulation kernel, called warped. warped is a publically available Time Warp simulation kernel for experimentation and application development. The kernel defines a standard interface to the application developer and is designed to provide a highly configurable environment for the integration of Time Warp optimizations. It is written in C++, uses the MPI message passing standard for communication, and executes on a variety of platforms including a network of SUN workstations, a SUN SMP workstation, the IBM SP1/SP2 multiprocessors, the Cray T3E, the Intel Paragon, and IBM-compatible PCs running Linux.

SAVANT/TyVIS/WARPED: components for the analysis and simulation of VHDL

The SAVANT, QUEST II, and HEPE research programs at the University of Cincinnati include the development and distribution of VHDL analysis and simulation capabilities. These capabilities are being freely distributed for non-commercial use. The SAVANT project is underway specifically to develop a VHDL analyzer with a well-documented, extensible intermediate form; the main objective is to smooth the integration of VHDL technology into university and industrial research programs. The SAVANT project is funded through the Air Force SBIR program and is a joint activity between the University of Cincinnati and MTL Systems, Inc. The QUEST II program is investigating parallel algorithms and architectures for simulation, behavioral synthesis, and ATPG. The HEPE program is investigating (in part) novel strategies for relaxing causal orders in the parallel simulation of active networks. As part of the QUEST II/HEPE simulation activities, a VHDL simulation kernel is being developed that will operate with the SAVANT intermediate form for sequential or parallel execution of VHDL models (a C++ code generator from the SAVANT intermediate is being jointly developed by the SAVANT and QUEST II programs). All of the software from the QUEST and HEPE simulation programs is freely available for use (commercial or otherwise).

Analysis and Simulation of Mixed-Technology VLSI Systems

Circuit simulation has proven to be one of the most important computer aided design (CAD) methods for verification and analysis of, integrated circuit designs. A popular approach to modeling circuits for simulation purposes is to use a hardware description language such as VHDL. VHDL has had a tremendous impact in fostering and accelerating CAD systems development in the digital arena. Similar efforts have also been carried out in the analog domain which has resulted in tools such as SPICE. However, with the growing trend of hardware designs that contain both analog and digital components, comprehensive design environments that seamlessly integrate analog and digital circuitry are needed. Simulation of digital or analog circuits is, however, exacerbated by high-resource (CPU and memory) demands that increase when analog and digital models are integrated in a mixed-mode (analog and digital) simulation. A cost-effective solution to this problem is the application of parallel discrete-event simulation (PDES) algorithms on a distributed memory platform such as a cluster of workstations. In this paper, we detail our efforts in architecting an analysis and simulation environment for mixed-technology VLSI systems. In addition, we describe the design issues faced in the application of PDES algorithms to mixed-technology VLSI system simulation.

SUAVE: extending VHDL to improve data modeling support

Our aim in the SUAVE (SAVANT and University of Adelaide VHDL Extensions) Project is to improve support for high-level modeling and reuse in VHDL. A number of previous proposals also address these goals. SUAVE extends the language with object-orientation and genericity features and generalizes some existing features. Extending VHDL in this way has the side effect of improving its expressiveness at all abstraction levels. We adapted most of the added features from Ada-95, largely for the same reasons they are included in that language.

Redesigning the WARPED simulation kernel for analysis and application development

WARPED is a publicly available time warp simulation kernel. The kernel defines a standard interface to the application developer and is designed to provide a highly configurable environment for the integration of time warp optimizations. It is written in C++, uses the MPI message passing standard, and executes on a variety of parallel and distributed processing platforms. Version 2.0 of WARPED described here is distributed with several applications and the configuration can be set so that a sequential kernel implementation can be instantiated The kernel supports LP clustering, various GVT algorithms, and numerous optimizations to adaptively adjust simulation parameters at runtime.

Integrating multiple parallel simulation engines for mixed-technology parallel simulation

The emergence of mixed-signal (analog and digital) integrated circuits motivates the need for CAD tools supporting mixed-signal design and analysis. Furthermore, the presence of a large body of existing models in existing modeling language and the need for modeling mixed-signal (analog and digital) circuits motivates the need for a single unified simulation framework into which different parallel simulation subsystems can be easily connected. In this paper we have review the design of a light-weight simulation backplane for integrating simulators from different domains. Of particular focus for this paper is the integration of a parallel SPICE (analog circuit) simulator called Xyce/sup TM/ with a parallel VHDL (digital circuit) simulator called SAVANT.

Reuse through genericity in SUAVE

VHDL currently has a limited form of genericity in which component and entity declarations can be parameterized with formal generic constants. SUAVE extends the genericity mechanism by allowing formal generics types and by allowing generics to be specified in the interfaces of subprograms and packages. The approach is based on the features of Ada-95. It allows units to be re-used in a much wider variety of contexts without modifying the original code. We show that the genericity added by SUAVE enhances reuse across the spectrum of modeling, from high-level to gate level. In particular, the genericity extensions interact with the SUAVE extensions for object-oriented data modeling to significantly improve support for high-level behavioral modeling and for developing test-benches. We show that the genericity extensions integrate seamlessly with the existing language. Furthermore, the implementation burden is not large, and since generic instantiation is performed at elaboration time, there is no performance penalty in simulation or synthesis.

Experiences in verifying parallel simulation algorithms

Parallelization is a popular technique for improving the performance of discrete event simulation. Due to the complex, distributed nature of parallel simulation algorithms, debugging implemented systems is a daunting, if not impossible task. Developers are plagued with transient errors that prove difEcult to replicate and eliminate. Recently, researchers at The University of Cincinnati developed a parallel simulation kernel, WARPED, implementing a generic parallel discrete event simulator based on the Tie Warp optimistic synchronization algorithm. The intent was to provide a common base from which domain specific simulators can be developed. Due to the complexity of the Tie Warp algorithm and the dependence of many simulators on the simulation kernel’s correctness, a formal specification was developed and verified for critical aspects of the Tie Warp system. This paper dexribes these specifications, their verification and their interaction with the development process.

DISCOE: distributed design and analysis to preserve intellectual property

The DISCOE project deploys a co-design environment to support distributed, collaborative design activities. The environment supports secure transmission of design data by remote analysis and execution (simulation) of vendor protected data. The analysis and simulation environment is platform independent and operates in a distributed, heterogeneous Web based computational platform. A distributed, searchable online library will promote design reuse and relieve the effect of parts obsolescence. Furthermore, the organization of DISCOE supports future expansion for other necessary analysis capabilities such as co-synthesis and support of HLA and man-in-the-loop simulation.