Venugopal Gopinathan

Background calibration of interleaved analog to digital converters for high-speed communications using interleaved timing recovery techniques

We introduce the interleaved timing recovery (ITR) technique, with the objective of compensating sampling time errors in interleaved arrays of analog to digital converters (ADC) in high-speed communications receivers. When combined with interleaved automatic gain control (IAGC) and offset compensation (IOC), also discussed, this technique effectively compensates the most important components of fixed pattern noise, an impairment of interleaved ADCs that limits their performance and applicability. This technique exploits functions that are already present in the receiver. By modifying these functions, they can be used to compensate the impairments. This technique compares favorably in terms of performance and hardware complexity with previously known analog and digital calibration techniques. Performance is demonstrated by computer simulation of a 12-bit, 8-way interleaved ADC array whose effective resolution is limited to 6 bits before compensation.