Vesa Lahtinen

Overview of bus-based system-on-chip interconnections

This paper introduces the basic properties, such as structure, transfer properties and arbitration of bus-based interconnections for System-on-Chip (SoC) designs. The overview shows that contemporary SoC buses differ only in minor details. As a result, practically every studied interconnection method could rather easily conform to a common interface. Such an interface would enhance design re-use and make system design easier. However, due to their similarity, the choice between buses is not a straightforward task.

HIBI Communication Network for System-on-Chip

This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection (HIBI) aims at maximum efficiency and minimum energy per transmitted bit combined with quality-of-service (QoS) in transfers. Other features include support for hierarchical topologies with several clock domains, flexible scalability, and runtime reconfiguration of network parameters. HIBI is intended for integrating coarse-grain components such as intellectual property (IP) blocks that have size of thousands of gates.HIBI has been implemented in VHDL and SystemC and synthesized on several CMOS technologies and on FPGA. A 32-bit wrapper requires 5400 gates and runs with 315 MHz on 0.18 μ m technology which shows that only minimal area overhead is paid for the advanced features. The area and frequency results are well comparable to other NoC proposals.Furthermore, data transfers are shown to approach the maximum theoretical performance for protocol efficiency. HIBI network is accompanied with a design framework with tools for optimizing the system through automated design space exploration.

HIBI v.2 Communication Network for System-on-Chip

This paper presents a communication network targeted for complex system-on-chip (SoC) and network-on-chip (NoC) designs. The Heterogeneous IP Block Interconnection v.2 (HIBI) aims at maximum efficiency and energy saving per transmitted bit combined with guaranteed quality-of-service (QoS) in transfers. Other features include support for arbitrary topologies with several clock domains, flexible scalablility in signalling and run-time reconfiguration of network parameters. HIBI has been implemented in VHDL and SystemC and synthesized in 0.18 CMOS technology with area comparable to other NoC wrappers. HIBI data transfers are shown to approach the maximum theoretical performance for protocol efficiency.

Benchmarking mesh and hierarchical bus networks in system-on-chip context

The performance and area of a System-on-Chip depend on the utilized communication method. This paper presents simulation-based comparison of generic, synthesizable single bus, hierarchical bus, and 2-dimensional mesh on-chip networks. Performance of the network depends heavily on the application and therefore six test cases with multiple parameter values are used. Furthermore, two versions of each network topology are compared. The results show that hierarchical bus scales well to large number of agents and offers a good performance and area trade-off although it has smaller aggregate bandwidth and area than mesh. Hierarchical HIBI bus achieves runtimes comparable to 2-dimensional cut-through mesh with about 50% smaller network logic. However, depending on the test case, the runtime can be reduced by 20-50% when wider bus links are utilized.

Comparison of synthesized bus and crossbar interconnection architectures

This paper presents a modular way to synthesize on-chip interconnection architectures for very large scale integrated (VLSI) systems using generic components. The components use a standard interface and, therefore, the functionality of the system can be designed separately from the architecture. Examples from different ends of the performance and cost spectrum are presented. A bus is a simple interconnection that is still powerful enough for many applications. When larger transmission bandwidths are needed, also a crossbar can be considered. The choice of the utilized network should be based on the requirements of the application. The most important metrics helping the decision process are interconnection area and throughput. A bus network is found to be considerably smaller in area than a crossbar but the throughput of a crossbar is over two times higher in large data transfers. The throughput of the examined complex crossbar is mainly bounded by arbitration latencies.

Interconnection scheme for continuous-media systems-on-a-chip

Abstract In this paper, an on-chip interconnection scheme called Heterogeneous IP Block Interconnection (HIBI) is presented. HIBI offers a scaleable and easy to use architecture for system-on-a-chip designs. Its most distinguishing feature is the lack of a central arbiter and specialized arbitration signals. The arbitration is distributed among the connected agents that are made aware of each others communication requirements. This enables data transmissions with very low latencies and also minimizes the amount of needed signal lines. These features make the scheme a good fit to continuous-media systems transmitting large amounts of streaming data. With the presented interconnection scheme, bus efficiencies greater than 90% have been achieved in several test cases. With the streaming burst transfers and time slot based accesses of HIBI, throughputs of over one data transmission per clock cycle are possible.

A communication-centric design flow for HIBI-based SoCs

This paper describes a design flow for Systems-on-Chip(SoCs) utilizing a previously presented HIBI communication network. The system designer is assisted with an automated two-level architecture exploration that optimizes the component allocation, task mapping and scheduling with static application analyses, and dynamic simulations. The utilization of a system-level model of computation enables fast analysis of the design and facilitates automated architecture exploration. Communication design is in a key role in the design flow since it is a critical part of contemporary SoCs. The platform of the design flow is based on the HIBI communication network that is easily scalable and parameterizable for a variety of communication requirements. As a result, the design flow selects the computational component from library, HIBI network instance and application mapping that optimizes the result of cost function. The designer assists the flow by defining the cost function and optimization control parameters as well as giving the architecture and mapping constraints.

Optimizing finite state machines for system-on-chip communication

In this paper, finite state machine (FSM) optimization for a system-on-chip (SoC) interconnection is presented. In the used interconnection architecture, the same interface block is used repeatedly and, therefore, optimization of the interface for synthesis is a very critical implementation issue. However, low-level hand-optimization is not desirable and, therefore, optimization should be performed in the high-level description or automatically in the synthesis process. The results of this paper suggest that design space exploration leads to substantial improvements when constructing complex SoCs. Ideas on how to support this automatically with FSM optimization are shown.

System Level Design Experiences and the Need for Standardization

The growing complexity of electronic systems has forced the adoption of new design methods operating on higher abstraction levels. These new methods include for example the utilization of virtual platforms in software development, the early exploration of architectures, management of platform complexity, system-level verification, and high-level synthesis of sub-modules of a system. In this paper, some of the issues encountered in adopting these design methods into production use are discussed. Based on the experiences gathered, it seems that the methods are still somewhat immature and, frequently, based on proprietary technologies. This calls for a unified effort from the design community to come into an agreement on the details of the methods and, consequently, drive these agreements into truly open standard solutions. From system house perspective, this is the only way these new design methods can be successful. The aim of this paper is to acknowledge three key system-level standardization forums: the Open SystemC Initiative (OSCI), the Open Core Protocol-International Partnership (OCP-IP), and the Structure for Packaging, Integrating and Re-using IP within Tool-flows (SPIRIT)

Bus Structures in Network-on-Chips

It seems obvious that there is no general interconnection that perfectly fits every arbitrary application. Particularly, the proposed homogeneous network topologies and fixed bus architectures have many limitations. Because application is rarely an exact fit to the architecture, the ratio of average throughput to maximum available throughput in these systems is relatively small. A heterogeneous architecture, which makes a further distinction between local and global communication, addresses some of these problems. Locally, in segments having only a few agents, the communication can be accomplished via a bus. On the other hand, the global communication topology between these segments should be based on application specific bus and network structures.